STMicroelectronics Inc v. Optical Licensing LLC

1. Case Identification

• Case #: IPR2021-01593
• Patent #: 6,791,898
• Filed: October 1, 2021
• Petitioner(s): STMicroelectronics, Inc.
• Patent Owner(s): Optical Licensing, LLC
• Challenged Claims: 1-18

2. Patent Overview

• Title: Memory Device Providing Asynchronous and Synchronous Data Transfer
• Brief Description: The ’898 patent discloses a memory device capable of operating in both synchronous and asynchronous data transfer modes. The purported novelty lies in utilizing dedicated asynchronous/synchronous logic coupled with a configuration register that allows for selection between the two transfer modes based on control signals.

3. Grounds for Unpatentability

Ground 1: Anticipation by Childs - Claims 1-7, 9, 10, 13, 15, and 18 are anticipated under 35 U.S.C. §102 by Childs.

• Prior Art Relied Upon: Childs (Patent 5,384,737).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Childs, which was not considered during prosecution, discloses every limitation of the challenged claims. Childs teaches a pipelined memory with selectable synchronous and asynchronous operating modes. Petitioner asserted that Childs’s “mode control circuit,” which receives an external mode signal and generates an internal control signal (ASYNC*), functions identically to the “configuration register” recited in independent claims 1 and 7. The state of the ASYNC* signal directly controls whether data passes through output registers dependent on clock signals (synchronous) or regardless of clock signals (asynchronous), thereby specifying the transfer mode as claimed. Dependent claims related to read/write modes are met by Childs’s disclosure of a write enable signal (W*) that controls the operation type.

Ground 2: Anticipation by Shiomi - Claims 1-10, 13, and 15-18 are anticipated under 35 U.S.C. §102 by Shiomi.

• Prior Art Relied Upon: Shiomi (Patent 5,124,589).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Shiomi, also not considered during prosecution, teaches a self-timed random access memory (STRAM) that can be switched between synchronous and asynchronous operation. The core of the argument is that Shiomi’s “input data retain circuit,” which receives a “through signal (TH),” is the claimed “configuration register.” When the TH signal is inactive, the circuit functions as a standard latch, retaining data synchronously with a clock signal. When the TH signal is active, the latching function is disabled, allowing data to pass through asynchronously. This direct control over the operational mode based on the TH signal was argued to meet the limitations of the independent claims for specifying the transfer mode.

Ground 3: Obviousness over Shiomi and Stephens - Claims 11, 12, and 14 are obvious over Shiomi in view of Stephens.

• Prior Art Relied Upon: Shiomi (Patent 5,124,589) and Stephens (Patent 5,548,560).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground targets claims that add limitations for reading or writing a "plurality of words" or a "burst of words." Petitioner argued that Shiomi teaches the fundamental selectable synchronous/asynchronous memory architecture but does not explicitly disclose burst mode operations. Stephens, however, is directed to a burst mode static random access memory (SRAM) that also provides for both synchronous and asynchronous data transfer. Petitioner argued that a person of ordinary skill in the art (POSITA) would have looked to a reference like Stephens to implement high-speed data access features like burst mode into the system taught by Shiomi.
  • Motivation to Combine: A POSITA would combine Stephens’s burst mode functionality with Shiomi's memory architecture to achieve Shiomi's stated objective of reducing cycle times and enabling high-speed data reading. The motivation was asserted to be particularly strong because Stephens expressly discusses Shiomi in its background section, demonstrating that a POSITA would have considered the two technologies together.
  • Expectation of Success: A POSITA would have a reasonable expectation of success in making this combination, as burst mode was a well-known and conventional technique for improving the speed and throughput of memory systems at the time of the invention.

• Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 1-10, 13, and 15-18 based solely on Shiomi as an alternative to the anticipation ground.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. §325(d), stating that the primary references (Childs and Shiomi) present art that is not cumulative to what was considered during prosecution. The examiner’s allowance was based on the configuration register limitation, which Petitioner contends is expressly taught by the new art.
• Petitioner also argued against discretionary denial under Fintiv, asserting that the co-pending district court actions were in very early stages with minimal investment from the parties or the court. It was highlighted that Petitioner is not a party to the co-pending litigations and that this inter partes review (IPR) challenges all 18 patent claims, whereas the district court cases involve only subsets of claims, positioning the IPR as a more efficient vehicle for resolving the patent's validity.

5. Relief Requested

• Petitioner requests institution of an IPR and cancellation of claims 1-18 of Patent 6,791,898 as unpatentable.