Oracle Corp v. Sonrai Memory Ltd

1. Case Identification

• Case #: IPR2022-00018
• Patent #: 6,829,691
• Filed: October 13, 2021
• Petitioner(s): Oracle Corp.
• Patent Owner(s): Sonrai Memory Limited
• Challenged Claims: 1-30

2. Patent Overview

• Title: System for Compressing/Decompressing Data
• Brief Description: The ’691 patent discloses systems and methods for data compression and decompression using a memory controller with integrated compression/decompression logic. The architecture features two separate busses connecting the controller to two distinct memory arrays, enabling simultaneous transfer of data (e.g., compressed data on one bus and uncompressed data on the other).

3. Grounds for Unpatentability

Ground 1: Obviousness over Dye and Aleksic - Claims 1-28 and 30 are obvious over Dye in view of Aleksic.

• Prior Art Relied Upon: Dye (Patent 6,173,381) and Aleksic (Patent 6,469,703).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Dye discloses an integrated memory controller (IMC) with a compression/decompression engine capable of performing memory-to-memory operations between two banks of system memory. However, the examiner in the original prosecution could not find art showing a dual-bus architecture for such a system. Petitioner asserted that Aleksic supplies this missing element by teaching a memory controller with two distinct memory channels (CH0, CH1), each a complete bus, for simultaneous access to separate memory banks. The combination maps to the claimed system of a memory controller with compression logic (Dye) coupled to two memory arrays via two distinct busses (Aleksic's channels).
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Dye and Aleksic to improve system performance and memory access speeds. Implementing Dye’s dual-bank memory system with Aleksic's true dual-channel architecture would accelerate operations like decompressing cached data from memory, a process taught by Dye, thereby reducing system latency.
  • Expectation of Success: A POSITA would have a high expectation of success, as the combination involves applying known dual-channel memory access techniques (Aleksic) to a known memory compression architecture (Dye) to achieve the predictable result of improved performance.

Ground 2: Obviousness over Dye, Aleksic, and Farmwald - Claim 29 is obvious over Dye and Aleksic in view of Farmwald.

• Prior Art Relied Upon: Dye (Patent 6,173,381), Aleksic (Patent 6,469,703), and Farmwald (Patent 5,319,755).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on the combination of Dye and Aleksic from Ground 1 to address the limitations of claim 29, which further requires control signals comprising a row address strobe (RAS) and a column address strobe (CAS). Petitioner contended the base combination of Dye and Aleksic teaches a memory controller that issues control signals over a control bus. Farmwald is introduced to explicitly teach that RAS and CAS are conventional control signals used to control memory arrays.
  • Motivation to Combine: A POSITA implementing the memory controller of Dye/Aleksic would naturally use standard, well-known memory control signals to interface with memory arrays. Farmwald shows that RAS and CAS were such standard signals, making their inclusion an obvious design choice for implementing the control bus portion of Aleksic’s channels.
  • Expectation of Success: The use of standard RAS/CAS signals as taught by Farmwald to control memory in the Dye/Aleksic system would be a routine and predictable implementation detail.

Ground 3: Obviousness over Belt and Aleksic - Claims 13-16 are obvious over Belt in view of Aleksic.

• Prior Art Relied Upon: Belt (Patent 5,974,471) and Aleksic (Patent 6,469,703).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner presented an alternative combination where Belt provides the base system. Belt discloses a memory controller with compression/decompression logic ("codec") that transfers data between a main memory (via a memory bus) and a CPU cache (via a CPU local bus). Petitioner argued that a POSITA would implement Belt's separate memory bus and CPU local bus using the two independent memory channels (CH0, CH1) taught by Aleksic. This combination teaches a method of transferring compressed data from main memory (first memory location) via a first bus (e.g., CH0) to the memory controller’s codec, decompressing it, and transferring the uncompressed data via a second bus (e.g., CH1) to the CPU cache (second memory location).
  • Motivation to Combine: A POSITA would combine Belt and Aleksic to improve the performance of Belt’s system. Aleksic's dual-channel architecture would increase memory access speeds and bandwidth, directly addressing the goal of Belt, which is to improve performance for real-time multimedia applications.
  • Expectation of Success: A POSITA would reasonably expect success in using Aleksic's known dual-bus memory access circuits to implement the data pathways in Belt's system to achieve the predictable result of increased data throughput.

4. Key Claim Construction Positions

• "logic for directing" (claim 1) and "selection logic" (claim 21): Petitioner argued that while the Patent Owner asserts these terms have a plain and ordinary meaning, the presumption against means-plus-function treatment should be overcome. Petitioner contended the terms fail to recite sufficiently definite structure to a POSITA and are merely generic substitutes for "means," thus requiring construction under 35 U.S.C. §112, sixth paragraph.
• "memory controller" (claims 1, 11, etc.): Petitioner proposed this term be construed as "a circuit that issues the electrical control and physical address signals to a memory that cause the memory to read or write data," asserting this was a well-known term of art at the time of the invention.

5. Arguments Regarding Discretionary Denial

• §314(a) (Fintiv Factors): Petitioner argued against discretionary denial, asserting that: (1) it intends to seek a stay in the parallel district court litigation; (2) the district court trial date is not yet set and is likely to slip past the IPR's Final Written Decision deadline; and (3) a stipulation to not pursue the same grounds in district court significantly reduces any issue overlap.
• §325(d) (Same or Substantially Same Art or Arguments): Petitioner argued strongly that denial under §325(d) is unwarranted because the petition presents prior art that corrects a clear error by the original examiner. Specifically, the examiner allowed the claims after being unable to find prior art for a dual-bus memory system—the very technology Petitioner asserted is clearly disclosed in Aleksic, which was never considered during prosecution. Because Aleksic and Belt are new references that directly address the perceived novel aspect of the invention, the examiner’s allowance was erroneous.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-30 of the ’691 patent as unpatentable.