Samsung Electronics Co Ltd v. Netlist Inc

1. Case Identification

• Case #: IPR2022-00063
• Patent #: 10,217,523
• Filed: October 15, 2021
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-34

2. Patent Overview

• Title: Multi-Mode Memory Module With Data Handlers
• Brief Description: The ’523 patent discloses a self-testing memory module containing a plurality of memory devices. The module uses a central control module to generate test signals and distributed "data handlers" that are located near corresponding memory devices to generate and verify test patterns.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ellsberry and Jeddeloh752 - Claims 1-34 are obvious over Ellsberry in view of Jeddeloh752

• Prior Art Relied Upon: Ellsberry (Application # 2006/0277355) and Jeddeloh752 (Patent 7,310,752).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ellsberry disclosed the fundamental architecture of the claimed memory module, including a central Control ASIC (analogous to the claimed "control module") and distributed Switch ASICs (analogous to the claimed "data handlers") that buffer data between memory devices and the system controller. However, Ellsberry lacked self-testing functionality. Petitioner asserted that Jeddeloh752, which taught a built-in self-test (BIST) system for memory, supplied the missing test features. The proposed combination involved integrating Jeddeloh752’s test-related address and control logic into Ellsberry’s Control ASIC and its data pattern generation and comparison logic into each of Ellsberry’s distributed Switch ASICs. This mapping allegedly satisfied the limitations of independent claims 1 and 19, which require a memory module with a control module and a data module capable of operating in a normal mode and a test (second) mode.
  • Motivation to Combine: Petitioner contended a person of ordinary skill in the art (POSITA) would combine these references to improve the reliability of Ellsberry’s high-speed memory modules, a known need at the time, particularly for emerging JEDEC standards that required self-testing. Distributing Jeddeloh752’s test functionality into Ellsberry’s existing distributed architecture was presented as a logical design choice to simplify implementation and minimize changes. Since Ellsberry’s Control ASIC already configured the memory devices, a POSITA would be motivated to add test control functionality to it directly rather than relying on the host system.
  • Expectation of Success: The combination was argued to be a predictable application of known testing techniques to a known memory architecture, yielding the expected result of a self-testing memory module without undue experimentation.

Ground 2: Obviousness over Ellsberry, Jeddeloh752, and Averbuj - Claims 1-34 are obvious over Ellsberry and Jeddeloh752 in further view of Averbuj

• Prior Art Relied Upon: Ellsberry (Application # 2006/0277355), Jeddeloh752 (Patent 7,310,752), and Averbuj (Application # 2005/0257109).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground augmented the primary combination with Averbuj to explicitly teach the "isolate" limitation found in claims 1, 11, and 32. Petitioner argued that Averbuj disclosed a modular BIST architecture using a multiplexer (MUX) to select between a normal data path from the system controller and a test data path from a pattern generator. This MUX functionality explicitly isolated the memory devices from the system memory controller during the BIST mode.
  • Motivation to Combine: A POSITA, having combined Ellsberry and Jeddeloh752, would be faced with two data sources (the system controller in normal mode and the internal pattern generators in test mode) needing to access the same memory device data pins. To prevent data collisions, a POSITA would be motivated to incorporate Averbuj’s well-known MUX-based switching mechanism to select between the two data paths, thus achieving the claimed isolation.

Ground 3: Obviousness over Ellsberry, Jeddeloh752, and Lee - Claims 14, 17-34 are obvious over Ellsberry and Jeddeloh752 in further view of Lee

• Prior Art Relied Upon: Ellsberry (Application # 2006/0277355), Jeddeloh752 (Patent 7,310,752), and Lee (Application # 2006/0095817).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground introduced Lee to address limitations in claims 14 and 17 requiring data patterns to be based on information received from the control module. Lee taught a method for testing memory where test patterns and associated input modes could be received from an off-module source via a system management bus (SMBUS). A pattern generator within the module would then generate test data "based on" this received information.
  • Motivation to Combine: Petitioner argued a POSITA would be motivated to implement Lee’s technique in the Ellsberry/Jeddeloh752 combination to enhance flexibility. This approach would reduce the local storage requirements within each Switch ASIC and allow test patterns to be more easily defined, maintained, or updated from a centralized, off-module location, resulting in a more robust and adaptable testing system.

• Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 14 and 17-34 based on the combination of Ellsberry, Jeddeloh752, Averbuj, and Lee, relying on similar motivations.

4. Key Claim Construction Positions

• "rank": Petitioner proposed construing "rank" as "an independent set of memory devices that act together in response to a memory command... to read or write the full bit-width of the memory module." This construction was argued to be consistent with the specification and necessary to understand how Ellsberry’s architecture, with its groups of DRAMs activated by chip-select signals, met the claim limitations.
• "data handler": Petitioner relied on a construction from a related district court case meaning "circuitry for generating and processing data." This construction was central to mapping Ellsberry’s "Switch ASICs" to the claimed data handlers and incorporating the test pattern generation functionality from Jeddeloh752.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §325(d) or §314(a) would be inappropriate. The petition asserted that the Board previously instituted trial on the same claims and grounds in a prior IPR (IPR2020-01421) involving a different petitioner (SK hynix), indicating the petition’s merits. That prior IPR was terminated due to settlement. Petitioner contended it was not involved in the prior IPR and had a license to the ’523 patent at the time, giving it no reason to join. Due to a subsequent change in circumstances regarding the license, Petitioner argued it now had a legitimate reason to file this petition. Further, Petitioner argued against denial under Fintiv, noting the only parallel proceeding was a recently filed declaratory judgment action for non-infringement, not invalidity.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-34 of Patent 10,217,523 as unpatentable.