Volkswagen Group Of America Inc v. Arigna Technology Ltd

1. Case Identification

• Case #: IPR2022-00147
• Patent #: 7,049,850
• Filed: November 9, 2021
• Petitioner(s): Volkswagen Group of America, Inc.
• Patent Owner(s): Arigna Technology Ltd.
• Challenged Claims: 1, 7, 8, 10, 13, and 20

2. Patent Overview

• Title: Semiconductor Device With A Voltage Detecting Device To Prevent Shoot-Through Phenomenon In First And Second Complementary Switching Devices
• Brief Description: The ’850 patent relates to a semiconductor device for driving a half-bridge switching circuit. The invention aims to prevent a "shoot-through" phenomenon—where high-side and low-side switches are simultaneously active, causing a short circuit—by using a voltage detecting device to monitor circuit conditions and control the switches.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1, 13, and 20 under 35 U.S.C. §102 over Wong

• Prior Art Relied Upon: Wong (Patent 6,037,720).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Wong, which discloses a semiconductor switched-bridge circuit, teaches every element of independent claims 1, 13, and 20. Wong’s circuit includes high-side (T1) and low-side (T2) switching devices, a high potential part with a control circuit for T1, and a low potential part with a low-side logic circuit (ANO circuit 114) that generates control signals to prevent shoot-through. Petitioner asserted that Wong’s pulse generator (134), level-shift parts (switches T3a/T3b with current sources Iia/Iib), and voltage detecting device (falling/rising edge detectors FED/RED) meet the corresponding limitations in claim 1. For claim 13, Petitioner mapped Wong’s low-side inverter (116') as the voltage detecting device in the low potential part. For claim 20, Petitioner mapped Wong’s high-side falling edge detector (FED1) as the voltage detecting device in the high potential part.

Ground 2: Anticipation of Claim 7 under 35 U.S.C. §102 over Orita

• Prior Art Relied Upon: Orita (Application # 2003/0012040).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Orita, which describes a power semiconductor device with fault protection, anticipates all limitations of independent claim 7. Orita disclosed a half-bridge circuit with high-side (SW1) and low-side (SW2) switches. Petitioner mapped Orita’s high-side circuitry (including output circuit OU) as the claimed "high potential part including a control part." Orita’s reverse level shift circuit (IS) was identified as the claimed "reverse level shift part" configured to send a signal from the high side to the low side. Finally, Petitioner argued Orita’s inverter (IV3) functions as the claimed "voltage detecting device" located in the high potential part, as it detects a potential from an output line of the reverse level shift part (the output of inverter IV1) and supplies a logic value to control the high-side switch SW1.

Ground 3: Obviousness of Claims 8 and 10 under 35 U.S.C. §103 over Orita in view of Sedra & Smith

• Prior Art Relied Upon: Orita (Application # 2003/0012040) and Sedra & Smith (a 1998 microelectronics textbook).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the assertion that Orita taught the elements of claim 7. Dependent claims 8 and 10 add specific structural details to the "voltage detecting device" (Orita’s inverter IV3), requiring it to be a MOS transistor with specific insulating films and, for claim 10, to be a complementary MOS (CMOS) pair. Petitioner argued that while Orita disclosed a generic inverter, it was obvious to implement it using a standard CMOS inverter design as taught by the Sedra & Smith textbook. Sedra & Smith allegedly taught the conventional structure of a CMOS inverter, including the use of NMOS and PMOS transistors, gate insulating films (e.g., silicon dioxide), and common gate electrodes, thereby satisfying the limitations of claims 8 and 10.
  • Motivation to Combine: A POSITA would combine these references to implement Orita's generic inverter (IV3) with a standard, well-known, and power-efficient CMOS design. Petitioner asserted this amounted to a simple and predictable substitution of a known element for another to improve a known device, consistent with Orita's goal of creating a low-cost, reliable device.
  • Expectation of Success: A POSITA would have had a high expectation of success, as implementing a fundamental logic gate with a standard CMOS architecture was a routine, predictable task for an electrical engineer at the time.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under both §314(a) (Fintiv) and §325(d) would be inappropriate.
• Regarding Fintiv, Petitioner asserted it had been diligent in filing, the IPR was filed before invalidity contentions were due in a parallel district court case, few resources had been expended in that litigation, and the IPR challenges a broader set of claims than the co-pending litigation.
• Regarding §325(d), Petitioner argued that denial was unwarranted because none of the asserted prior art references (Wong, Orita, or Sedra & Smith) were considered by the examiner during the original prosecution of the ’850 patent.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1, 7, 8, 10, 13, and 20 of Patent 7,049,850 as unpatentable.