PTAB

IPR2022-00283

Amazon.com Inc v. Swarm Technology LLC

Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: System and Method for Parallel Processing Using Dynamically Configurable Proactive Co-Processing Cells
  • Brief Description: The ’004 patent relates to a distributed processing architecture comprising a controller, a task pool, and multiple co-processors. The system is designed for parallel processing where co-processors proactively and independently retrieve tasks from the task pool, execute them, and update the pool upon completion without direct communication with the controller.

3. Grounds for Unpatentability

Ground 1: Obviousness over Lurie - Claim 1 is obvious over Lurie

  • Prior Art Relied Upon: Lurie (Application # 2007/0124363).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lurie discloses every element of claim 1. Lurie’s distributed computing system includes a Technical Computing Client (TCC) that functions as the claimed controller, an Automatic Task Distribution (ATD) Mechanism that serves as the claimed task pool, and multiple Technical Computing Workers (TCWs) that act as the claimed co-processors. Petitioner asserted that Lurie’s TCWs retrieve tasks from, and return results to, the ATD Mechanism without communicating directly with the TCC controller. Furthermore, Lurie’s disclosure that TCWs can dynamically register with the ATD Mechanism to become available for tasks was argued to teach the "plug-and-play" limitation of the claim.
    • Expectation of Success: As all limitations were allegedly taught by the single Lurie reference, a person of ordinary skill in the art (POSITA) would have had a high expectation of success.

Ground 2: Obviousness over Lurie and Ethernet Specification - Claims 2-3 and 6-11 are obvious over Lurie in view of Ethernet Specification

  • Prior Art Relied Upon: Lurie (Application # 2007/0124363) and Ethernet Specification (a 1980 technical standard).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on the teachings of Lurie to address dependent claims requiring "agents" and task-type differentiation. Petitioner contended that a POSITA implementing Lurie’s networked system would use a standard protocol like Ethernet. The Ethernet Specification discloses data frames containing a source address, destination address, and a data payload, which Petitioner argued are analogous to the claimed "agents." Lurie teaches that TCWs (co-processors) can be configured for specific task types based on their characteristics. Petitioner asserted it would be obvious to use the payload of an Ethernet data frame to carry information identifying a task type (e.g., a function pointer), allowing the agent to search Lurie's task pool for an appropriate task.
    • Motivation to Combine: A POSITA would combine Lurie with the Ethernet Specification because Lurie explicitly discloses its system components communicating over network links, including LANs. At the time, Ethernet was the ubiquitous and logical standard for implementing such a LAN, making its use a predictable design choice to enable the networked communication described by Lurie.
    • Expectation of Success: The combination involved applying a well-known, standard networking protocol to a known distributed computing architecture, which would have been a routine and predictable task for a POSITA.

Ground 3: Obviousness over Lurie, Ethernet Specification, and Sander - Claims 4-5 are obvious over Lurie in view of Ethernet Specification and Sander

  • Prior Art Relied Upon: Lurie (Application # 2007/0124363), Ethernet Specification (a 1980 technical standard), and Sander (Application # 2012/0192201).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground addresses dependent claims 4 and 5, which recite specific physical layouts of system components on monolithic integrated circuits (ICs). Claim 4 requires the controller and task pool to reside on one IC while the co-processors are on separate ICs; claim 5 requires all components to reside on a single IC. Petitioner argued that while Lurie does not specify physical layout, Sander, which describes an analogous processing system, explicitly teaches both configurations. Sander discloses that its CPU (controller) and queue (task pool) can be formed on a single silicon die either with its processing cores (co-processors) or separately from them.
    • Motivation to Combine: A POSITA implementing Lurie's system would look to similar art like Sander for known design choices regarding component layout to optimize performance. Sander addresses the same technical problem of efficient workload balancing. Applying Sander’s teaching would allow a designer to either reduce latency by co-locating the controller and task pool (claim 4) or maximize integration and speed for specific applications by placing all components on a single chip (claim 5).
    • Expectation of Success: Applying known IC layout options from Sander to the analogous architecture in Lurie represented a predictable substitution of known elements with a high expectation of success.
  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claim 12 based on Lurie, Ethernet Specification, and Chow but relied on a similar design modification theory to add a processor availability check.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that the Board should not exercise discretionary denial under Fintiv. It was asserted that the co-pending district court case involving the Petitioner is stayed and in its earliest stages, with no trial date set and minimal discovery or investment, weighing heavily in favor of institution.
  • Petitioner also argued against denial under §325(d), contending that the primary prior art references asserted in the petition (Lurie, Sander, and Chow) were not considered during the original prosecution and are not the same as or substantially the same as art previously presented to the Office.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-12 of Patent 9,852,004 as unpatentable.