PTAB

IPR2022-00432

Broadcom Corp v. Monterey Research LLC

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Controlling Drive Strength of Microcontroller I/O Nodes
  • Brief Description: The ’753 patent discloses systems for controlling the drive strength of a microcontroller's input/output (I/O) node. The invention uses arrays of reconfigurably selectable pull-up and pull-down resistors to dynamically adjust the voltage and current characteristics at an I/O pin.

3. Grounds for Unpatentability

Ground 1: Obviousness over Arcoleo and Goetting - Claims 1, 3-6, 13, 15, 16, 18, and 19 are obvious over Arcoleo in view of Goetting.

  • Prior Art Relied Upon: Arcoleo (Patent 5,732,027) and Goetting (Patent 5,877,632).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Arcoleo taught an output buffer circuit for a semiconductor memory device with a selectable drive strength controlled by multiple pull-up and pull-down transistors. While Arcoleo focused on an output buffer, Petitioner contended Goetting supplied the missing "input/output" functionality. Goetting expressly disclosed a configurable input/output buffer for a Field Programmable Gate Array (FPGA) with selectable pull-up and pull-down elements. The combination of Arcoleo's selectable drive strength mechanism with Goetting's I/O pin and buffer structure allegedly rendered the limitations of independent claim 1 obvious.
    • Motivation to Combine: A POSITA would combine Arcoleo and Goetting because both addressed the same problem of controlling drive strength in similar semiconductor devices. Petitioner noted that Arcoleo itself suggested its applicability to FPGAs, the specific subject matter of Goetting. A POSITA would therefore be motivated to apply Arcoleo's drive strength control to Goetting's established I/O structure to achieve the predictable result of an I/O node with variable drive strength, an improvement that would increase efficiency.
    • Expectation of Success: A POSITA would have had a high expectation of success as the combination involved applying a known technique (Arcoleo's drive strength control) to a similar device (Goetting's I/O buffer) for its intended purpose.

Ground 2: Obviousness over Goetting - Claims 1, 3-6, 13, 15, 16, 18, and 19 are obvious over Goetting in view of the knowledge of a person of ordinary skill in the art.

  • Prior Art Relied Upon: Goetting (Patent 5,877,632).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Goetting alone disclosed nearly all elements of the challenged claims. Goetting described a configurable I/O buffer for an FPGA comprising an I/O pin, a plurality of configurable pull-ups (e.g., PMOS transistors or resistors), and a plurality of configurable pull-downs. These elements were shown to be selectable by logic (configuration bits in memory cells) to control the drive strength of the I/O node and implement different I/O standards.
    • Motivation to Combine: For dependent claims requiring a "mode register" (claims 5, 6, and 16), which Goetting did not explicitly name, Petitioner argued it would have been obvious for a POSITA to use this well-known component. Citing other prior art as evidence of the state of the art, Petitioner contended a POSITA would readily implement Goetting's configuration logic using a standard mode register to control the selection of pull-up and pull-down elements.
    • Expectation of Success: A POSITA would expect success in using a well-known component like a mode register for its conventional purpose of storing configuration data to control the selection logic already present in Goetting's circuit.

4. Key Claim Construction Positions

  • Petitioner argued the term "resistor" must be construed as an "element (or combination of elements) that implements electrical resistance." This construction was presented as crucial because the primary prior art references, Arcoleo and Goetting, primarily disclose transistors (e.g., MOSFETs) rather than discrete resistors to perform the pull-up and pull-down functions. Petitioner asserted this broader construction was required by the ’753 patent’s own specification and dependent claims (e.g., claims 3 and 4), which explicitly state that the claimed "resistors" are implemented as n-MOS and p-MOS devices.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv, contending that the parallel district court litigation was in its nascent stages. Key points included that no firm trial date had been set, investment by the court and parties was minimal, and a pending motion to transfer filed by Petitioner could cause further delays in the court proceeding. Petitioner also asserted that the strong merits of the invalidity grounds presented in the petition weighed in favor of institution to promote efficiency and avoid potentially conflicting outcomes.

6. Relief Requested

  • Petitioner requests the institution of an inter partes review (IPR) and cancellation of claims 1, 3-6, 13, 15, 16, 18, and 19 of Patent 6,573,753 as unpatentable under 35 U.S.C. §103.