IPR2022-00564
Samsung Display Co Ltd v. Bishop Display Tech LLC
1. Case Identification
- Case #: IPR2022-00564
- Patent #: 6,906,769
- Filed: February 10, 2022
- Petitioner(s): Samsung Display Co., Ltd.
- Patent Owner(s): Bishop Display Tech LLC
- Challenged Claims: 1, 5, 6, 11, and 14
2. Patent Overview
- Title: Liquid Crystal Screen Display
- Brief Description: The ’769 patent discloses an active matrix liquid crystal display (LCD) designed to restrain "display unevenness." The invention involves a structure where gate signal lines, acting as a first conductive member, are in partial contact with an alignment layer and have a negative voltage applied to them to generate ions and create a more uniform ion concentration within the liquid crystal layer.
3. Grounds for Unpatentability
Ground 1: Claims 1, 5, 6, 11, and 14 are obvious over Shimada in view of Kaneko.
- Prior Art Relied Upon: Shimada (Japanese Published Patent Application No. H8-95075) and Kaneko (Patent 4,909,602).
- Core Argument for this Ground:
Prior Art Mapping: Petitioner argued that Shimada, which was not considered during prosecution, discloses every structural limitation of independent claim 1. Shimada teaches an active matrix LCD with a first insulating substrate, a second insulating substrate, a liquid crystal layer, and corresponding alignment layers. Critically, Petitioner asserted that Shimada discloses the key feature of a "first conductive member being gate signal lines" which is "formed on the first insulating substrate," "interposed between the first insulating substrate and its corresponding alignment layer," and in "partial contact with the alignment layer." The only limitation of claim 1 not explicitly taught by Shimada is the application of a "negative voltage" to these gate signal lines.
For the dependent claims, Petitioner contended that Shimada also discloses their additional limitations. Specifically, Shimada teaches a "light blocking layer" that overlaps with the first conductive member (claim 5), a "second conductive member" (common electrode) disposed between the second substrate and its alignment layer (claims 6 and 11), and the overlap of this second conductive member with the light blocking layer (claim 14).
Motivation to Combine (for §103 grounds): Petitioner argued that a person of ordinary skill in the art (POSITA) would combine Kaneko’s teachings with Shimada's device to arrive at the claimed invention. Shimada does not specify a driving voltage scheme for its LCD. Kaneko addresses the problem of improving image quality in a structurally similar active matrix LCD by preventing erroneous thin-film transistor (TFT) turn-on. Kaneko teaches applying a gate-off voltage that is lower than the minimum source signal line voltage (a "negative voltage" as construed by Petitioner). A POSITA would recognize that Shimada’s TFTs would face the same parasitic capacitance issues as Kaneko's and would be motivated to apply Kaneko’s known, beneficial voltage scheme to Shimada’s device to achieve the predictable result of improved image quality and signal holding.
Expectation of Success (for §103 grounds): Given the structural similarities of the LCDs and TFTs in Shimada and Kaneko, and the predictable electrical principles involved, a POSITA would have had a reasonable expectation of success in applying Kaneko's driving method to Shimada's display to improve its performance.
4. Key Claim Construction Positions
- "negative voltage": Petitioner argued this term should be construed according to its express definition in the ’769 patent specification. This definition requires the voltage applied to the gate signal lines (when the TFT is OFF) to be "lower than the lowest voltage" applied to the source signal lines during that same period. Petitioner contended that Kaneko's taught gate-off voltage (VNS), which is lower than the minimum data signal voltage (VDMIN), squarely meets this definition and is the key to the obviousness combination.
5. Arguments Regarding Discretionary Denial
- Petitioner argued against discretionary denial under §314(a) and the Fintiv factors. It contended that the parallel district court proceeding was at an early stage, with no claim construction hearing held, minimal discovery completed, and a trial date that was uncertain due to the large number of asserted patents (13) and other cases on the court's docket. Petitioner also highlighted a lack of overlap, as it was challenging unasserted claims (6, 11, 14) and offered a stipulation not to pursue the same grounds or prior art in district court if the inter partes review (IPR) was instituted. Finally, Petitioner asserted the petition presented a strong case for unpatentability, as the primary prior art (Shimada) was not before the examiner and disclosed the key structural features added during prosecution to overcome prior rejections.
6. Relief Requested
- Petitioner requested institution of an IPR and cancellation of claims 1, 5, 6, 11, and 14 of the ’769 patent as unpatentable.