PTAB

IPR2022-00645

OpenSky Industries LLC v. VLSI Technology LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Minimum Memory Operating Voltage Technique
  • Brief Description: The ’373 patent relates to a method and system for managing power in an integrated circuit (IC) by dynamically providing regulated voltages to a memory. The invention addresses scenarios where a processor may operate at a lower voltage than its associated memory, ensuring the memory receives sufficient voltage to prevent data loss even as the processor's voltage fluctuates for power savings.

3. Grounds for Unpatentability

Ground 1: Obviousness over Harris, Abadeer, and Zhang - Claims 1-7, 9-11, and 13-16 are obvious over Harris in view of Abadeer and Zhang.

  • Prior Art Relied Upon: Harris (Patent 5,867,719), Abadeer (Application # 2006/0259840), and Zhang (Application # 2003/0122429).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued the combination of these references discloses all elements of the challenged claims. Harris teaches the core architecture: an IC with a processor and memory where a switching circuit dynamically selects between a first primary voltage (VDD) and a second standby voltage (Vstby) to power the memory. Abadeer teaches a method for determining a memory’s minimum operating voltage using a built-in self-test (BIST) and storing this value in non-volatile memory (e.g., fuses). Zhang discloses using integrated voltage regulators to provide stable, adjustable supply voltages to different functional circuits within an IC to manage power consumption, a technique known as dynamic voltage scaling.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine these references to create a more robust and efficient power management system. A POSITA would use Abadeer’s method for determining a precise minimum operating voltage to implement the vague "set level or threshold" in Harris, thereby improving the reliability of Harris's low-power and failure-protection modes. A POSITA would further incorporate Zhang’s voltage regulators to provide the stable and controllable regulated voltages required for the dynamic voltage adjustments described in Harris, which Harris itself does not detail. This combination would achieve predictable improvements in power management.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success, as the combination involves applying known techniques (minimum voltage testing, voltage regulation) to a known system architecture (dynamic power supply switching) to achieve the predictable result of improved power efficiency and data retention.

Ground 2: Obviousness over Harris, Abadeer, Zhang, and Cornwell - Claims 2, 11, and 12 are obvious over the combination of Ground 1 and Cornwell.

  • Prior Art Relied Upon: Harris (Patent 5,867,719), Abadeer (Application # 2006/0259840), Zhang (Application # 2003/0122429), and Cornwell (Patent 7,702,935).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground adds Cornwell to address limitations in claims 2, 11, and 12 requiring testing for a group of minimum voltages, including minimum write voltage, minimum read voltage, and minimum standby voltage. While Abadeer teaches testing for a minimum standby voltage, Cornwell explicitly teaches determining and recording minimum read and write operating voltages for a memory during the manufacturing process.
    • Motivation to Combine: A POSITA would be motivated to incorporate Cornwell’s teachings to achieve more granular power savings. By determining the specific minimum voltages required for different memory operations (read, write, standby), the system could operate closer to the true minimum required voltage for any given task, thereby maximizing power efficiency beyond what a single standby voltage threshold would allow. This was a known strategy for power reduction.

Ground 3: Obviousness over Harris, Abadeer, Zhang, and Bilak - Claim 8 is obvious over the combination of Ground 1 and Bilak.

  • Prior Art Relied Upon: Harris (Patent 5,867,719), Abadeer (Application # 2006/0259840), Zhang (Application # 2003/0122429), and Bilak (Application # 2005/0188230).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground adds Bilak to address the limitation in claim 8, which requires that the minimum operating voltage is determined by "performing a test applied externally from the integrated circuit." Bilak expressly discloses that determining the minimum operating voltage ("Vmin") of an IC is a well-known technique that is typically performed "by an external tester during manufacturing test."
    • Motivation to Combine: A POSITA would recognize that performing this test externally (per Bilak) is a simple and predictable design choice and an obvious alternative to using an internal BIST (per Abadeer). Since both internal and external testing were well-known, predictable, and interchangeable methods for determining minimum operating voltages, choosing one over the other would have been an obvious matter of design preference.

4. Key Claim Construction Positions

  • Petitioner argued that most claim terms should be given their plain and ordinary meaning.
  • For the means-plus-function term in claim 14, "means for providing the operating voltage...", Petitioner contended the structure should be construed as a "power supply selector," consistent with a district court construction. Petitioner argued that the switch circuit disclosed in Harris satisfies this construction, and that the adjustable voltage regulators taught by Zhang satisfy the slightly broader construction proposed by the Patent Owner in the parallel litigation.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial would be inappropriate. The petition asserted that under the General Plastic factors, which govern follow-on petitions, this case should proceed because Petitioner is unrelated to prior petitioners (Intel, Patent Quality Assurance) and is not holding back art, instead promoting efficiency by raising the same grounds as a co-pending petition.
  • Petitioner further argued against discretionary denial under Fintiv, noting that a prior IPR filed by Intel was denied on procedural Fintiv grounds, not on the merits of the prior art. Crucially, the jury in the parallel district court litigation, which resulted in a $1.5 billion verdict against Intel, was not asked to consider the patent's validity. Therefore, Petitioner argued that review is necessary to ensure the integrity of the patent system.

6. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-16 of the ’373 patent as unpatentable.