Nokia Corp v. TQ Delta LLC

1. Case Identification

• Case #: IPR2022-00664
• Patent #: 7,844,882
• Filed: March 4, 2022
• Petitioner(s): Nokia of America Corporation
• Patent Owner(s): TQ Delta, LLC
• Challenged Claims: 9-16

2. Patent Overview

• Title: Shared Memory Allocation for Interleaver and Deinterleaver
• Brief Description: The ’882 patent discloses a system for managing memory in a Digital Subscriber Line (DSL) transceiver. The core technology involves dynamically allocating portions of a common, shared memory between an interleaver (for transmitting data) and a deinterleaver (for receiving data) to improve efficiency and reduce hardware requirements.

3. Grounds for Unpatentability

Ground 1: Obviousness over Mazzoni and VDSL1 - Claims 9-16 are obvious over Mazzoni in view of VDSL1.

• Prior Art Relied Upon: Mazzoni (Patent 7,269,208) and VDSL1 (ETSI TS 101 270-2 Very High Speed Digital Subscriber Line technical specification).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Mazzoni taught a VDSL transceiver system with a shared memory that is allocated between an interleaver and a deinterleaver. Mazzoni further disclosed calculating the required memory size based on factors like bit rate and impulse noise, and using Reed-Solomon (RS) coded data. However, Petitioner contended Mazzoni did not explicitly disclose an initialization message specifying a maximum number of bytes available for allocation. VDSL1, a technical standard for the VDSL environment described in Mazzoni, allegedly supplied this missing element by teaching an initialization protocol between transceivers that includes transmitting a message (R-MSG2) containing a "Maximal interleaver memory" field, which specifies this exact capability.
  • Motivation to Combine: A POSITA implementing Mazzoni’s VDSL system would have been motivated to consult the VDSL1 standard for necessary implementation details, such as standard-compliant initialization protocols. Mazzoni expressly stated its invention could be applied to a VDSL environment, making VDSL1 a natural and necessary reference for a skilled artisan to ensure interoperability and proper function. The combination would allow the transceivers in Mazzoni to communicate their hardware capabilities and negotiate parameters, a known benefit of initialization.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because both references operated in the same VDSL field and contemplated the same triangular implementation of convolutional interleaving, using identical parameters (I and M) to calculate memory size.

Ground 2: Obviousness over VDSL1 and Fadavi-Ardekani - Claims 9-16 are obvious over VDSL1 in view of Fadavi-Ardekani.

• Prior Art Relied Upon: VDSL1 (ETSI TS 101 270-2) and Fadavi-Ardekani (Patent 6,707,822).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that VDSL1 taught a standard VDSL transceiver system that determines memory allocations for an interleaver and deinterleaver and uses an initialization protocol to communicate maximum memory capabilities. However, VDSL1 did not explicitly teach using a shared memory architecture. Fadavi-Ardekani allegedly supplied this teaching, disclosing a transceiver for DSL systems that used a shared memory (IDIM) between the interleaver and deinterleaver in a "ping-pang" fashion. This method was presented as a known technique to increase efficiency, support more data-intensive sessions, and reduce costs.
  • Motivation to Combine: A POSITA implementing the VDSL1 standard would have been motivated to incorporate the shared memory architecture of Fadavi-Ardekani to achieve known efficiencies and cost reductions. Since the VDSL1 standard required supporting various data rates and sessions, implementing a shared memory was a known way to meet these performance parameters efficiently. Fadavi-Ardekani expressly taught that its invention could be beneficially implemented with VDSL, directly suggesting the combination.
  • Expectation of Success: A POSITA would expect success because both references were directed to DSL systems and disclosed compatible components, including Reed-Solomon encoding, interleavers, and deinterleavers. Combining a known hardware efficiency technique (Fadavi-Ardekani) with a governing technical standard (VDSL1) was a straightforward design choice.

4. Key Claim Construction Positions

• "transceiver": Petitioner argued the district court improperly narrowed this term to require the transmitter and receiver portions to "share at least some common circuitry." Petitioner contended the plain and ordinary meaning should control, as the patent specification disclosed embodiments where only transmitter portions shared memory, meaning the transmitter and receiver portions would not necessarily share common circuitry.
• "shared memory": Petitioner also disputed the district court's construction of "common memory used by at least two functions, where a portion of the memory can be used by either one of the functions." Petitioner advocated for the term's plain and ordinary meaning, arguing it was improper to import this functional limitation from the specification into the claim.
• Overall Stance: For both terms, Petitioner argued that even under the district court's narrower constructions, the challenged claims were still rendered obvious by the asserted prior art combinations.

5. Arguments Regarding Discretionary Denial

• Arguments against §325(d) Denial (Advanced Bionics): Petitioner argued that denial would be improper because the core prior art combinations were not previously before the USPTO. Specifically, VDSL1 was a new reference not considered during prosecution. Petitioner asserted this created a material difference from the Examiner's analysis, which had concluded that the closest prior art (Fadavi-Ardekani) failed to teach elements that VDSL1 now supplied.
• Arguments against §314(a) Denial (Fintiv): Petitioner argued that the Fintiv factors weighed against discretionary denial. Key reasons included that the co-pending district court litigation was in a very early stage, with no substantive rulings on the ’882 patent and a trial date far in the future. Further, Petitioner stipulated that, if the IPR were instituted, it would not pursue the same invalidity grounds in the district court, thus preventing duplicative efforts. Finally, the grounds presented in the petition were materially different from those previously considered by a jury in separate litigation involving different parties and different prior art.

6. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 9-16 of Patent 7,844,882 as unpatentable under 35 U.S.C. §103.