PTAB

IPR2022-00744

Micron Technology Inc v. Netlist Inc

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1. Case Identification

2. Patent Overview

  • Title: Memory Module with Data Buffering
  • Brief Description: The ’314 patent discloses a memory module, such as a Dual In-Line Memory Module (DIMM), that includes ranks of memory devices and register buffers separating the devices from the memory controller. The technology addresses the timing consequence of this architecture, where the addition of register buffers results in an overall Column Address Strobe (CAS) latency for the module that is greater than the actual operational CAS latency of the individual memory integrated circuits.

3. Grounds for Unpatentability

Ground 1: Claims 1-2, 6, 8, and 12-14 are obvious over Halbert

  • Prior Art Relied Upon: Halbert (Application # 2002/0112119).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Halbert discloses a memory module architecture that meets all limitations of the challenged claims. Halbert’s memory module (100) includes a data interface circuit (120) with registers (126, 128) positioned between memory ranks (140, 142) and the system memory bus. This circuitry responds to memory commands (e.g., READ/WRITE) from a controller (20) to transfer bursts of N-bit wide data signals and data strobes. Petitioner asserted that Halbert’s timing diagrams show these data transfers are registered and that the interface circuit is configured to add a predetermined time delay (e.g., one clock cycle), making the overall module CAS latency greater than the operational latency of the memory devices, as required by claim 1.
    • Prior Art Mapping (Dependent Claims): Petitioner further contended that Halbert discloses isolating the memory devices from the capacitive loading of the system bus (claim 2), using data paths that function as logic pipelines (claim 6), specifying an N-bit width of 64 bits (claim 8), and using synchronous DRAMs that transfer data on both edges of a data strobe (claims 13-14).
    • Motivation to Combine (for §103 grounds): This ground relies on a single reference, with motivation derived from Halbert’s own teachings and the knowledge of a person of ordinary skill in the art (POSITA) to recognize the disclosed features.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success as all elements were allegedly disclosed within Halbert’s integrated system design.

Ground 2: Claims 3 and 9-10 are obvious over Halbert in view of JESD21-C

  • Prior Art Relied Upon: Halbert (Application # 2002/0112119) and JESD21-C (JEDEC Standard 21-C, Jan. 2002).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that while Halbert provides the fundamental memory module architecture, the JESD21-C industry standard for registered DIMMs supplies conventional teachings for specific implementations not explicitly detailed in Halbert. For claim 3, JESD21-C was cited to show the standard use of input chip select signals that are received by a register and output as registered chip select signals to select between different memory ranks. For claims 9 and 10, Petitioner pointed to JESD21-C’s disclosure of a standard DIMM architecture comprising a 72-bit wide rank constructed from eighteen 4-bit wide memory integrated circuits arranged in nine pairs, with each pair configured to communicate a byte of data, thereby simulating an 8-bit wide memory device.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Halbert’s memory module design with the teachings of the contemporaneous JESD21-C standard to ensure industry compliance, interoperability, and to implement well-known, standardized memory configurations. Both references are directed at improving SDRAM module design.
    • Expectation of Success (for §103 grounds): Success would have been expected, as this combination involves integrating predictable, standard-compliant features into Halbert's compatible architecture.

Ground 3: Claim 5 is obvious over Halbert in view of JESD79-2A

  • Prior Art Relied Upon: Halbert (Application # 2002/0112119) and JESD79-2A (JEDEC Standard JESD79-2A, Jan. 2004).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted this combination renders claim 5 obvious. While Halbert teaches the core module, JESD79-2A, a JEDEC standard for DDR2 SDRAM, teaches the use of On-Die Termination (ODT). JESD79-2A describes ODT as a feature that allows a DRAM controller to turn termination resistance on or off via an ODT control signal to improve signal integrity. This teaching allegedly meets the limitations of claim 5, which require the memory module to be configured to receive an ODT signal and for the memory circuits to include an ODT circuit.
    • Motivation to Combine (for §103 grounds): A POSITA would be motivated to incorporate the ODT feature described in the JESD79-2A standard into Halbert’s high-speed memory module to address the known and critical problem of maintaining signal integrity.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success, as adding ODT functionality was a known and predictable solution for improving performance in advanced memory systems.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial would be inappropriate under both 35 U.S.C. §314(a) (Fintiv factors) and §325(d).
  • Fintiv Factors: Petitioner contended that denial is not warranted because the parallel district court litigation is in a very early stage and is currently stayed for all purposes other than claim construction. Furthermore, Petitioner stipulated that it will not pursue the same grounds or prior art references in the district court if the IPR is instituted, mitigating concerns of overlap and inefficiency.
  • §325(d) Factors: Petitioner argued that the Examiner committed material error during prosecution. Although Halbert and JESD21-C were submitted in an Information Disclosure Statement, the record shows they were never substantively evaluated, as no rejections were ever issued. The reference JESD79-2A was never before the Examiner. Petitioner asserted this oversight is material, particularly because the Board has previously relied on Halbert and JESD21-C to find claims unpatentable in related patents from the same family.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 5-6, 8-10, and 12-14 of the ’314 patent as unpatentable.