PTAB

IPR2022-00745

Micron Technology Inc v. Netlist Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Module with Data Buffering
  • Brief Description: The ’314 patent discloses a memory module, such as a dual in-line memory module (DIMM), connectable to a computer’s memory controller. The module includes ranks of memory devices and register buffers that separate the memory devices from the memory controller, which adds a clock cycle time delay and results in an overall Column Address Strobe (CAS) latency greater than the actual operational latency of the memory devices.

3. Grounds for Unpatentability

Ground 1: Obviousness over Halbert and JESD21-C - Claims 15-20 and 22-33 are obvious over Halbert in view of JESD21-C.

  • Prior Art Relied Upon: Halbert (Application # 2002/0112119) and JESD21-C (JEDEC Standard 21-C, Jan. 2002).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Halbert discloses the core architecture of the challenged claims. Halbert teaches a memory module with a module controller (logic) and interface circuitry that buffers data transfers between memory ranks and the system memory bus. This buffering introduces a one-clock-cycle delay, explicitly teaching the core limitation of an overall module CAS latency that is greater than the actual operational CAS latency of the memory devices themselves. Petitioner asserted that Halbert discloses nearly all limitations of independent claim 15, including the printed circuit board, logic receiving input signals and outputting registered signals, memory devices arranged in ranks, and circuitry coupled between the memory bus and the memory devices. For limitations not explicitly detailed in Halbert, such as specific memory device configurations (e.g., 18 4-bit devices per rank for a 72-bit bus as required by dependent claim 18) or the use of four chip select signals (claim 19), Petitioner contended that JESD21-C provides these teachings. JESD21-C is an industry standard for DDR SDRAM Registered DIMMs that discloses these exact configurations as common, standard designs. For example, JESD21-C's "Raw Card Version N" shows a design with two physical banks (ranks) of eighteen 4-bit wide memory devices configured in pairs to simulate 8-bit devices, providing for 72-bit-wide data transfers.
    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine Halbert and JESD21-C because both references are in the same field of SDRAM memory modules and address improving their design. A POSITA implementing Halbert’s memory module architecture would have been motivated to consult and comply with an industry-wide standard like JESD21-C to ensure compatibility, interoperability, and predictable performance. Modifying Halbert’s general architecture to incorporate specific, standardized design parameters from JESD21-C, such as chip select configurations or memory device arrangements, was presented as a simple matter of applying known industry standards to a known architecture, representing a predictable design choice rather than an inventive step.
    • Expectation of Success: Petitioner asserted that a POSITA would have had a reasonable expectation of success in combining the teachings. The combination involved applying a well-defined industry standard (JESD21-C) to a compatible memory architecture (Halbert), which would have yielded predictable results. Such a modification was argued to be one of a finite number of well-known solutions for designing standard-compliant memory modules.

4. Arguments Regarding Discretionary Denial

  • §314(a) (Fintiv Factors): Petitioner argued against discretionary denial under Fintiv based on a parallel district court case. The key arguments were that the parallel proceeding was in a very early stage with no trial date set and the litigation was stayed for all purposes other than claim construction. Furthermore, Petitioner submitted a stipulation that, if the IPR is instituted, it would not pursue the same grounds or prior art references in the district court case, thereby mitigating concerns of inefficiency and overlap. Petitioner contended these factors, combined with the strong merits of the petition, weigh heavily in favor of institution.
  • §325(d) (Same or Substantially the Same Prior Art): Petitioner argued that discretionary denial under §325(d) was not warranted because the Examiner made a material error by failing to substantively consider the asserted prior art during the prosecution of the ’314 patent. Although Halbert and JESD21-C were cited in an Information Disclosure Statement (IDS), the prosecution record is silent as to their relevance, and the Examiner issued a Notice of Allowance without any rejections. Petitioner asserted that this oversight was material, as the Board itself had previously relied on these same references (Halbert in IPR2017-00549 and JESD21-C in other IPRs) to find claims unpatentable in patents from the same family as the ’314 patent.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and cancellation of claims 15-20 and 22-33 of the ’314 patent as unpatentable.