Qualcomm Inc v. Monterey Research LLC

1. Case Identification

• Case #: IPR2022-00754
• Patent #: 6,979,640
• Filed: March 24, 2022
• Petitioner(s): QUALCOMM Incorporated
• Patent Owner(s): Monterey Research, LLC
• Challenged Claims: 1-17

2. Patent Overview

• Title: Semiconductor Interconnection Structures
• Brief Description: The ’640 patent discloses methods for making semiconductor structures, specifically for forming electrical connections ("vias") between conducting layers of an integrated circuit. The invention purports to solve issues with via misalignment by using a conformal etch-stop layer, which allows for the creation of "borderless vias" without space-consuming landing pads while preventing over-etching and yield loss.

3. Grounds for Unpatentability

Ground 1: Claims 1-6, 8-14, 16, and 17 are obvious over Liu in view of Havemann

• Prior Art Relied Upon: Liu (Patent 6,015,751) and Havemann (a 2001 technical overview titled "High-Performance Interconnects").
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Liu addresses the same problem as the ’640 patent—forming "unlanded via holes" without misalignment issues—using the same solution of a conformal etch-stop layer between the lower conducting layer and an interlayer dielectric. Petitioner argued Liu discloses all steps of independent claims 1 and 8, including forming a hole through a dielectric, extending it through an etch-stop layer to expose a conducting layer, and the key dimensional limitation. Specifically, Petitioner contended that Liu’s disclosed range for etch-stop layer thickness (30-300 nm) and conductor line width (250-500 nm) inherently discloses and makes obvious the claimed ratio where the etch-stop thickness is at least one-half the line width. For dependent claims, Havemann was introduced to teach common semiconductor manufacturing elements, such as using liners in via holes and specific materials (e.g., titanium, aluminum, copper, oxide, nitride) for various layers to improve reliability and prevent diffusion.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Liu with Havemann to implement Liu's method using well-known, reliable materials and structures for improved performance. For example, a POSITA would use Havemann's barrier metal liners to promote adhesion and prevent diffusion of conductive material into the dielectric layers of Liu's structure, which was a standard practice for enhancing device reliability.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success, as combining Havemann's conventional materials and structural enhancements with Liu's fabrication method involved applying known techniques to improve a known process.

Ground 2: Claims 1-17 are obvious over Liu and Lynch, in view of Havemann

• Prior Art Relied Upon: Liu (Patent 6,015,751), Lynch (a 1978 IEEE paper titled "The Reduction of LSI Chip Costs By Optimizing The Alignment Yields"), and Havemann.
• Core Argument for this Ground:
  • Prior Art Mapping: This ground reinforces Ground 1, arguing that even if Liu does not explicitly compel the claimed dimensional ratio, the combination with Lynch makes it obvious. Petitioner argued that the ’640 patent itself is based on the "Lynch equation" from the Lynch paper, which provides a mathematical formulation for maximizing alignment yield. Lynch taught that to ensure proper alignment and achieve nearly 100% yield, the space on each side of a conducting layer (analogous to the thickness of the conformal etch-stop layer in Liu) should be at least one-half the minimum feature size of that conducting layer. Petitioner asserted this is precisely the dimensional limitation that led to the allowance of the ’640 patent claims.
  • Motivation to Combine (for §103 grounds): A POSITA implementing Liu's method for creating borderless vias would be motivated to maximize yield, a primary concern in semiconductor manufacturing. A POSITA would naturally turn to a well-known, fundamental teaching like Lynch's to optimize the dimensions of Liu’s etch-stop layer. The goal was to achieve the benefits of miniaturization (taught by Liu) without sacrificing yield (the problem addressed by Lynch).
  • Expectation of Success (for §103 grounds): A POSITA would expect success in applying Lynch's established mathematical principles to Liu's physical structure, as both relate to the fundamental problem of alignment tolerance in photolithography.

Ground 3: Claims 1-17 are obvious over Maniar and Lynch, in view of Havemann

• Prior Art Relied Upon: Maniar (Patent 5,702,981), Lynch (1978 IEEE paper), and Havemann.
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner presented Maniar as an alternative primary reference that, like Liu, teaches the same solution to the same problem as the ’640 patent. Maniar explicitly discloses using a conformal etch-stop layer to prevent over-etching caused by misalignment when forming unlanded vias. Petitioner argued Maniar teaches every limitation of the independent claims except the specific dimensional ratio. As in Ground 2, Petitioner asserted that Lynch provides the missing dimensional teaching. Applying Lynch's principle for maximizing yield would lead a POSITA to size Maniar's etch-stop layer to be at least one-half the width of the underlying conductor.
  • Motivation to Combine (for §103 grounds): The motivation is identical to that in Ground 2: a POSITA seeking to optimize the yield of Maniar's process would be motivated to apply the fundamental and well-known teachings of Lynch to determine the optimal thickness for Maniar's etch-stop layer.
  • Expectation of Success (for §103 grounds): The combination of Maniar's structure with Lynch's optimization principles would be a straightforward application of known concepts to achieve a predictable improvement in manufacturing yield.
• Additional Grounds: Petitioner asserted additional obviousness challenges based on the combination of Maniar and Liu (with Havemann), arguing a POSITA would have been motivated to combine Maniar’s process with Liu’s specific dimensional teachings to achieve predictable results.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under Fintiv is inappropriate. It asserted that the co-pending district court litigation is in a very early stage, with trial scheduled for well after a Final Written Decision in the IPR would be due. Petitioner also contended that a separate IPR petition filed by Broadcom should not preclude institution because the petitioners are unrelated, are not co-defendants, and this petition presents prior art and arguments not included in the Broadcom petition.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-17 of Patent 6,979,640 as unpatentable.