PTAB

IPR2022-00756

LG Electronics Inc v. Sonrai Memory Ltd

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Multiprocessing Chip Utilizing Multiple Operating Systems
  • Brief Description: The ’014 patent describes a multiprocessing system where multiple processors mounted on a single chip are connected to a memory that stores multiple operating systems. The system is designed to allow different processors to execute different operating systems, with some processors capable of simultaneously executing multiple operating systems through methods like context switching.

3. Grounds for Unpatentability

Ground 1: Obviousness over Asano and Joy - Claims 1-3, 5-9, 11-13, and 15-19 are obvious over Asano in view of Joy.

  • Prior Art Relied Upon: Asano (Application # 2001/0044817) and Joy (Patent 6,542,991).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Asano taught a multiprocessing computer system with multiple processors (CPUs 11a-11n) connected to a memory storing multiple operating systems (OS-1 to OS-n). Asano also disclosed allocating processors to different operating systems and simultaneously running multiple operating systems. However, Asano did not explicitly teach mounting its processors on a single die. Joy was cited to cure this deficiency, as it disclosed a processor architecture that "combines multiple processors on a single integrated circuit die" to increase performance, reduce latency, and accelerate context switching. Petitioner asserted that the combination of Asano's multi-OS architecture with Joy's single-die implementation met the limitations of independent claims 1, 7, and 12.
    • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would combine Joy’s single-die multiprocessor architecture with Asano’s system to gain the well-known and predictable benefits of improved performance, reduced communication latency, and smaller physical size. Petitioner argued that Joy's teachings of accelerated context switching (down to nanosecond ranges) would be particularly advantageous for Asano’s system, which reallocates processors between different operating systems. Both references relate to improving computer systems for server applications, providing a strong reason to combine their teachings.
    • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success because combining multiple processors on a single die was a well-known, conventional design choice with predictable benefits, as acknowledged by the ’014 patent itself.

Ground 2: Obviousness over Asano and Babaian - Claims 1-3, 5-9, 11-13, and 15-19 are obvious over Asano in view of Babaian.

  • Prior Art Relied Upon: Asano (Application # 2001/0044817) and Babaian (Patent 7,143,401).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground used Asano as the primary reference for the same reasons as in Ground 1. To supply the "single die" limitation, Petitioner relied on Babaian instead of Joy. Babaian disclosed a "single chip multiprocessor system" with multiple processors contained on a single chip to substantially increase performance. Babaian also taught a system for the "flexible assignment" of its processors to execute different programs simultaneously. The combination of Asano’s multi-OS system with Babaian's single-chip, flexible-assignment processor architecture allegedly rendered the challenged claims obvious.
    • Motivation to Combine (for §103 grounds): The motivation was similar to Ground 1. A POSITA would have been motivated to implement Asano’s system using Babaian’s single-chip multiprocessor to achieve the known benefits of increased performance and efficiency. Furthermore, Babaian's teaching of flexible processor assignment to different tasks would have been seen as a natural fit for Asano's system, which allocates processors to different operating systems, allowing for faster and more efficient switching.
    • Expectation of Success (for §103 grounds): The combination involved implementing a known system (Asano) with a conventional hardware configuration (Babaian's single-chip multiprocessor) to achieve the foreseeable result of a more compact and higher-performance system, leading to a reasonable expectation of success.

4. Key Claim Construction Positions

  • Petitioner argued that several terms in means-plus-function claim 12 required construction.
  • "processor means for executing a plurality of operating system means": Petitioner proposed this be construed as "a chip multiprocessor having multiple processors mounted on a single die, or equivalents thereof," based on the specification's disclosure.
  • "operating system means": Petitioner proposed this be construed as "a conventional operating system, such as WINDOWS NT, UNIX, and the like, or equivalents thereof."
  • "memory means for storing said plurality of operating system means": Petitioner proposed this be construed as "SRAM and/or DRAM on the same chip as one or more processors; SRAM and/or DRAM on separate chips connected to one or more processors; magnetic media, such as tape or disk; optical media, such as CD-ROM; or equivalents thereof."

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under §314 and §325(d) would be inappropriate. The petition was filed with a motion for joinder to a previously instituted IPR filed by Google LLC (IPR2021-01454) that challenged the same claims of the ’014 patent on the same grounds. Petitioner noted that the Board had already declined to exercise its discretion to deny institution in the Google IPR and argued that, for similar reasons, it should institute and join the present proceeding to promote efficiency and avoid inconsistent results.

6. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-3, 5-9, 11-13, and 15-19 of the ’014 patent as unpatentable.