Microsoft Corp v. ThroughPuter Inc

1. Case Identification

• Case #: IPR2022-00757
• Patent #: 10,963,306
• Filed: March 30, 2022
• Petitioner(s): Microsoft Corp.
• Patent Owner(s): ThroughPuter, Inc.
• Challenged Claims: 1-24

2. Patent Overview

• Title: Managing Resource Sharing in a Multi-Core Data Processing Fabric
• Brief Description: The ’306 patent relates to techniques for managing and connecting tasks of parallelized programs running on multi-stage, many-core processor architectures. The disclosed system aims to achieve high resource efficiency and data throughput when sharing reconfigurable hardware resources among multiple user applications.

3. Grounds for Unpatentability

Ground 1: Claims 1-24 are obvious over Nollet in view of Tuan and Miller

• Prior Art Relied Upon: Nollet (Application # 2009/0187756), Tuan (a 2009 study on multitasking processors), and Miller (Patent 8,296,434).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that the core invention was a predictable combination of known elements. Nollet was argued to teach a multi-processor computing platform using a reconfigurable device, like a Field Programmable Gate Array (FPGA), for dynamic multitasking. Nollet’s example involved reallocating hardware resources from a movie decoder task to a 3D gaming task. Petitioner argued Tuan supplemented this by teaching the mapping of applications onto reconfigurable "tiles" as multi-stage, pipelined tasks interconnected by communication paths like first-in first-out (FIFO) buffers. Miller was asserted to teach a formal load-adaptive allocation policy, disclosing a "Dynamic Computing Scaling (DCS) Load Balancer" that monitors demand and reallocates computing nodes (including FPGAs) to different tasks accordingly. The combination allegedly discloses a multi-user system where processing units are linked for multi-stage programs (Nollet and Tuan) and reallocated based on demand under a load-adaptive policy (Nollet and Miller).
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Nollet with Tuan to implement a more structured, pipelined approach to multitasking, improving throughput and managing inter-task communication in Nollet's system. A POSITA would have been further motivated to incorporate Miller’s explicit load-balancing system to enhance Nollet’s resource management, thereby creating a more robust system that reallocates resources based on monitored demand to achieve greater efficiency—a well-known goal in the field.
  • Expectation of Success: Petitioner contended that combining these elements involved applying known techniques (pipelined task mapping, load balancing) to a known type of system (reconfigurable hardware) to yield the predictable result of improved efficiency and resource management.

Ground 2: Claims 1-24 are obvious over Nollet, Tuan, and Miller in view of Redaelli

• Prior Art Relied Upon: Nollet (Application # 2009/0187756), Tuan (a 2009 study on multitasking processors), Miller (Patent 8,296,434), and Redaelli (a 2010 workshop paper on task scheduling for multi-FPGA systems).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground incorporated all arguments from Ground 1 and added Redaelli to specifically address the claim limitation requiring a load-adaptive policy that "facilitate[s] minimizing reconfiguring the plurality of reconfigurable logic-based processing units." While the base combination (Nollet-Tuan-Miller) taught a load-adaptive policy, Petitioner argued Redaelli explicitly taught a scheduling solution for multi-FPGA systems designed to minimize reconfiguration. Redaelli’s method achieves this by looking for "module reuse opportunities" and leaving existing configurations "intact on the FPGA until other tasks require their space, in order to increase the probability of reuse."
  • Motivation to Combine: Petitioner asserted that a POSITA, already motivated by Nollet and Miller to create an efficient and fair resource allocation system, would naturally look to well-known optimization strategies. Minimizing reconfiguration is a known method to reduce latency and improve performance in such systems. Therefore, a POSITA would have been motivated to integrate Redaelli's scheduling approach, which prioritizes module reuse, into the load-adaptive framework of the Nollet-Tuan-Miller combination to achieve this desired optimization.
  • Expectation of Success: Adding a known scheduling optimization (module reuse) to a load-balancing system for reconfigurable hardware was presented as a straightforward design choice with a high expectation of achieving the predictable benefit of reduced latency.

4. Arguments Regarding Discretionary Denial

• Against Fintiv Denial (§314(a)): Petitioner argued against discretionary denial under Fintiv, asserting that the co-pending district court litigation was in its infancy with no established trial date, minimizing concerns about judicial efficiency. Petitioner further stipulated that it would not pursue in district court the same invalidity grounds raised in the IPR petition, which would prevent duplicative efforts and overlapping issues between the two forums.
• Against §325(d) Denial: Petitioner contended that denial under 35 U.S.C. §325(d) was unwarranted. Although the primary reference, Nollet, was considered by the USPTO during prosecution, Petitioner argued it was being presented in a "new light" in combination with three art references (Tuan, Miller, and Redaelli) that were never before the examiner. Petitioner asserted that this new art combination addresses limitations that were added via an Examiner's Amendment late in prosecution, which were critical to allowance. Thus, the examiner never had the opportunity to consider the patentability of the claims in view of these specific teachings.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-24 of Patent 10,963,306 as unpatentable.