PTAB

IPR2022-00801

Texas Instruments Inc v. Sonrai Memory Ltd

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Multiprocessing Chip Utilizing Multiple Operating Systems
  • Brief Description: The ’014 patent describes a multiprocessing system featuring multiple processors mounted on a single semiconductor die. These processors are connected to a memory that stores and runs multiple distinct operating systems, allowing different processors or groups of processors to execute different operating systems simultaneously.

3. Grounds for Unpatentability

Ground 1: Obviousness over Asano and Joy - Claims 1-3, 5-9, 11-13, and 15-19 are obvious over Asano in view of Joy.

  • Prior Art Relied Upon: Asano (Application # 2001/0044817) and Joy (Patent 6,542,991).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Asano taught the core elements of the ’014 patent, including a multiprocessing system with multiple CPUs connected to a memory storing and executing multiple operating systems (OS). Asano described allocating processor groups to different operating systems, including an active OS and a standby OS running simultaneously. However, Petitioner contended Asano did not explicitly disclose mounting its multiple processors on a single die. To supply this limitation, Petitioner cited Joy, which disclosed a processor architecture that "combines multiple processors on a single integrated circuit die" to enhance performance, increase parallelism, and accelerate context switching to nanosecond speeds. The combination of Asano's multi-OS management with Joy's single-die multiprocessor architecture was alleged to render the key limitations of independent claims 1, 7, and 12 obvious.
    • Motivation to Combine: Petitioner asserted a person of ordinary skill in the art (POSITA) would combine Joy’s single-die architecture with Asano’s multi-OS system to achieve predictable benefits. These benefits included reduced system size, lower communication latency between processors, and increased processing speed, all of which were well-known advantages of single-chip multiprocessors. Furthermore, Joy’s fast context switching capabilities would directly enhance the performance of Asano's system, which relied on switching processors between different operating systems.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in this combination because it involved applying a known hardware implementation (Joy's single-die multiprocessor) to a known software architecture (Asano's multi-OS system) to achieve foreseeable performance improvements without changing the fundamental operation of either.

Ground 2: Obviousness over Asano and Babaian - Claims 1-3, 5-9, 11-13, and 15-19 are obvious over Asano in view of Babaian.

  • Prior Art Relied Upon: Asano (Application # 2001/0044817) and Babaian (Patent 7,143,401).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative to Ground 1, using Babaian instead of Joy to supply the "single die" limitation missing from Asano. As in the first ground, Asano provided the foundational multi-processor, multi-OS system. Petitioner argued that Babaian taught a "single chip multiprocessor system" with multiple processors contained on one chip to substantially increase performance via parallel execution. Babaian further disclosed a system for the "flexible assignment" of its processors to execute different program tasks. Petitioner argued that combining Asano’s system with Babaian’s single-chip design rendered the challenged claims obvious.
    • Motivation to Combine: The motivation to combine Asano and Babaian was similar to that for combining Asano and Joy. A POSITA would be motivated to implement Asano’s system using Babaian’s single-chip design to gain significant, known performance benefits, improve data exchange efficiency, and reduce the physical footprint of the hardware. Babaian’s disclosure of flexibly assigning processors to tasks would have been seen as complementary to Asano’s method of allocating processors to different operating systems.
    • Expectation of Success: Petitioner argued that success would be expected, as this combination merely implemented a known multi-OS software architecture on a more efficient, well-understood single-chip hardware platform. The integration was a straightforward application of conventional computer design principles.

4. Key Claim Construction Positions

  • Petitioner argued that claim 12 contains three means-plus-function terms requiring construction under 35 U.S.C. §112, ¶ 6.
    • “processor means”: Construed as "a chip multiprocessor having multiple processors mounted on a single die, or equivalents thereof," based on the structure disclosed in the specification for performing the function of executing a plurality of operating systems.
    • “operating system means”: Construed as "a conventional operating system, such as WINDOWS NT, UNIX, and the like, or equivalents thereof."
    • “memory means”: Construed as "SRAM and/or DRAM on the same chip as one or more processors; SRAM and/or DRAM on separate chips connected to one or more processors; magnetic media...; optical media...; or equivalents thereof."

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv was inappropriate for several reasons.
    • The petition was filed as a request for joinder to an already-instituted IPR (IPR2021-01454) that relied on the same grounds, demonstrating a reasonable likelihood of success.
    • The Final Written Decision would issue more than four months before the scheduled trial date in the parallel district court litigation.
    • Investment in the parallel litigation was minimal, as fact discovery had not yet commenced.
    • Petitioner stipulated that, if the IPR was instituted, it would not pursue the same invalidity grounds in the district court litigation, thus avoiding duplicative efforts and conserving judicial resources.

6. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-3, 5-9, 11-13, and 15-19 of the ’014 patent as unpatentable.