PTAB

IPR2022-00996

Samsung Electronics Co Ltd v. Netlist Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Flash-DRAM Hybrid Memory Module
  • Brief Description: The ’918 patent discloses a memory module that includes both volatile (SDRAM) and non-volatile (flash) memory. The module features an on-board power system with multiple converters (e.g., buck, dual buck) to generate several regulated voltages required by its components and is configured to transfer data from the volatile to non-volatile memory in the event of a power failure.

3. Grounds for Unpatentability

Ground 1: Obviousness over Harris and FBDIMM Standards - Claims 1-3, 8, 14-15, and 23 are obvious over Harris in view of the FBDIMM Standards.

  • Prior Art Relied Upon: Harris (Application # 2006/0174140) and FBDIMM Standards (JEDEC standards JESD82-20 and JESD205).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Harris teaches a memory module, specifically a Fully Buffered DIMM (FBDIMM), with an on-board voltage regulator to generate various local voltage levels from an external supply. The FBDIMM Standards, which define the specifications for the exact type of module disclosed in Harris, teach the specific regulated voltages required for the module's components, including the SDRAM devices (e.g., 1.8V), the advanced memory buffer (e.g., 1.5V), and serial presence detect memory (e.g., 3.3V). The combination thus disclosed a memory module with multiple regulated voltages supplied by on-board converters, meeting the core limitations of independent claims 1 and 23.
    • Motivation to Combine: A POSITA implementing the FBDIMM system of Harris would have been directly motivated to consult the corresponding JEDEC FBDIMM Standards to determine the precise, standardized voltages required for proper operation.
    • Expectation of Success: Petitioner asserted there was a high expectation of success, as combining a system with its governing industry standard is a routine and necessary step in product design.

Ground 2: Obviousness over Harris, FBDIMM Standards, and Amidi - Claims 1-30 are obvious over the combination of Ground 1 and Amidi.

  • Prior Art Relied Upon: Harris (Application # 2006/0174140), FBDIMM Standards, and Amidi (Patent 7,724,604).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on the Harris/FBDIMM combination by adding Amidi, which teaches a power management block for a memory module. Amidi's system monitors the input voltage and, upon detecting a power fault or disruption, switches to a battery backup to ensure a stable power supply. Petitioner contended this addition supplies the limitations of claims requiring a voltage monitor circuit that produces a trigger signal in response to the input voltage falling below or exceeding a threshold (claims 5-7, 9).
    • Motivation to Combine: Harris expressly recognized concerns with power reliability and proposed adding a "redundant" power source. A POSITA would combine the Harris/FBDIMM module with Amidi's well-known battery backup and voltage monitoring techniques to improve the module's reliability, which was a known problem with a predictable solution.
    • Expectation of Success: The combination involved applying a known power backup technique (Amidi) to a standard memory module (Harris/FBDIMM) to achieve the predictable result of improved data integrity during power disruptions.

Ground 4: Obviousness over Spiers and Amidi - Claims 1-30 are obvious over Spiers in view of Amidi.

  • Prior Art Relied Upon: Spiers (Application # 2006/0080515) and Amidi (Patent 7,724,604).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Spiers is remarkably similar to the ’918 patent, disclosing a backup device on a PCI card with volatile (SDRAM) memory, non-volatile (NAND flash) memory, a processor, and a backup power supply (capacitors) to move data from volatile to non-volatile memory upon power failure detection. While Spiers provided the core architecture, Amidi provided teachings for implementing such a system with specific, standardized DDR SDRAM, including its power management logic and voltage requirements.
    • Motivation to Combine: A POSITA implementing the backup system of Spiers would have been motivated to use commercially available, standardized memory like DDR2 or DDR3 SDRAMs. They would consult art like Amidi and the relevant JEDEC standards to learn the specific voltage and power management requirements for these components, making the combination a logical design choice.
    • Expectation of Success: Implementing a known architecture (Spiers) with standardized components and power management schemes (taught by Amidi and JEDEC) would have presented a high likelihood of success.
  • Additional Grounds: Petitioner asserted additional obviousness challenges by adding Hajeck (Patent 6,856,556) to the combinations of Ground 2 and Ground 4. Hajeck was primarily cited for its explicit teaching of a voltage detection circuit that detects both undervoltage and overvoltage conditions to further support the obviousness of claims requiring such functionality.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under §325(d), stating that the asserted prior art combinations were not presented to or considered by the USPTO during prosecution. While one reference (Spiers) was in an Information Disclosure Statement, it was part of a list of over 100 references and never substantively discussed by the Examiner.
  • Petitioner also argued that discretionary denial under Fintiv is unwarranted because the two co-pending district court cases involving the ’918 patent were in their infancy. At the time of filing, no trial dates were set, and no discovery requests had been served.

5. Relief Requested

  • Petitioner requests that the Board institute an inter partes review and cancel claims 1-30 of the ’918 patent as unpatentable under 35 U.S.C. §103.