PTAB

IPR2022-01031

Mercedes Benz Group Ag Mercedes Benz USA LLC v. Arigna Technology Ltd

Key Events

Petition

petition

Title: Semiconductor Device for Driving a Half Bridge-Type Switching Circuit
Brief Description: The ’850 patent discloses a semiconductor device for driving a half-bridge switching circuit used in high-voltage applications. The technology centers on a voltage detecting device that monitors potential at a node between a high-side and a low-side power transistor (e.g., IGBT) to prevent circuit damage from conditions like "shoot-through" or "ground fault" phenomena.

Prior Art Relied Upon: Majumdar (Application # 2003/0030394).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Majumdar discloses every element of independent claims 7 and 13. Majumdar describes a "power device controller" with first and second switching devices (transistors Q1 and Q2) connected in series between high and low main power potentials. Its circuit includes a "high potential part" containing a control circuit (3B) that controls the high-side switching device (Q1). Majumdar further discloses a "reverse level shift part" (transistor QLV3) that transmits a signal from the high potential part to a low-side logic circuit, and a "voltage detecting device" (latch circuit RT) in the high potential part that detects a potential at an output line of the reverse level shift part and supplies a corresponding logic value to the control circuit to manage the high-side device.

Prior Art Relied Upon: Majumdar (Application # 2003/0030394) and Sedra (a 1998 microelectronics textbook).
Core Argument for this Ground:
- Prior Art Mapping: This ground primarily addressed independent claim 20 and its dependent claims. Claim 20 recites a voltage detecting device that includes at least one MOS transistor whose operation is controlled by a potential from the low potential part. Petitioner contended that while Majumdar discloses the functional voltage detecting device (latch circuit RT), it does not specify the underlying transistor technology. Sedra, a widely used textbook, teaches that RS flip-flops, like the latch circuit in Majumdar, are commonly implemented using complementary MOS (CMOS) technology, which consists of PMOS and NMOS transistors.
- Motivation to Combine: A POSITA would combine Majumdar's high-level circuit design with Sedra's well-known, standard technique for implementing the specific components of that circuit. Applying Sedra's teachings on CMOS implementation to Majumdar's latch circuit RT was a routine and predictable design choice to create a functional device.
- Expectation of Success: Because implementing latch circuits using CMOS technology was a common and well-understood practice, a POSITA would have had a high expectation of success in applying Sedra's teachings to Majumdar's circuit.

Prior Art Relied Upon: Majumdar (Application # 2003/0030394).
Core Argument for this Ground:
- Prior Art Mapping: This ground presented an alternative obviousness theory for claim 13 and the primary theory for claim 1. Petitioner argued that while Majumdar explicitly places its voltage detecting device (latch circuit RT) in the high potential part, a POSITA would have found it obvious to place this component in the low potential part instead. The high and low potential parts represent a finite number of available locations for the component.
- Motivation to Combine: The motivation was simple design choice. A POSITA would have recognized that placing the latch circuit in either the high or low potential part were two alternative, functionally equivalent implementations. For instance, implementing the circuit in the low potential part could shorten interconnect trace lengths, minimizing parasitic capacitance and improving detection speed.
- Expectation of Success: A POSITA would have a reasonable expectation of success because moving the latch circuit to the low potential part is a simple design modification that would not alter its fundamental function of providing a logic value based on a detected potential to control the overall circuit operation.

Petitioner stated that its invalidity grounds are consistent with claim constructions issued by the U.S. District Court for the Eastern District of Texas in a related case. Key constructions relied upon include:
- "high main power potential" (Claim 7): "higher of two power supply potentials provided to the semiconductor device"
- "high potential part" (Claim 7): "high potential section"
- "a reverse level shift part" (Claim 7): "a section of the semiconductor device comprising one or more components for reverse level shifting"

Petitioner argued that the Board should not exercise discretionary denial under either Fintiv or 35 U.S.C. §325(d).
- Fintiv Factors: Petitioner contended that the Fintiv factors weigh strongly in favor of institution because the parallel district court case against them was voluntarily dismissed by the Patent Owner. As a result, Petitioner is not a party to any ongoing litigation with a scheduled trial date that would overlap with the IPR proceeding.
- §325(d): Petitioner argued that denial under §325(d) is inappropriate because the primary prior art references, Majumdar and Sedra, were not before the examiner during the original prosecution of the ’850 patent. Therefore, the petition raised new, non-cumulative arguments that warrant consideration.

Petitioner requests the institution of an inter partes review and the cancellation of claims 1-2, 4, 7-8, 10, 13, 15, 17, 20, 22, and 24 of Patent 7,049,850 as unpatentable.