Samsung Electronics Co Ltd v. Netlist Inc

1. Case Identification

• Case #: IPR2022-01428
• Patent #: 8,787,060
• Filed: August 26, 2022
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-34

2. Patent Overview

• Title: Method and Apparatus for Optimizing Driver Load in a Memory Package
• Brief Description: The ’060 patent relates to reducing the electrical load of drivers in memory packages. The technology involves replacing a single data driver with two or more drivers coupled to the same data terminal, where each driver is responsible for driving a data signal to a distinct subset of stacked array dies via a separate die interconnect.

3. Grounds for Unpatentability

Ground 1: Claims 1-6, 8-14, 16-19, and 29-34 are obvious over Kim in view of Rajan.

• Prior Art Relied Upon: Kim (Application # 2011/0103156) and Rajan (Patent 8,041,881).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kim disclosed the foundational structure of the challenged claims: a memory package with a control die (main chip C0) and multiple stacked array dies (slave chips C1, C2) organized into distinct groups. Each group is connected to the control die via a separate through-silicon via (TSV), which functions as the claimed "die interconnect." Kim’s control die includes a control circuit (rank selecting unit) that controls data conduits between a data terminal (DQ pad) and the respective TSVs in response to control signals. Rajan was argued to supply the missing details for making Kim’s structure a fully functional, JEDEC-compliant memory module. Specifically, Rajan taught using a buffer chip (analogous to Kim’s control die) to interface with a host system, manage stacked DRAM chips, and emulate JEDEC standards, including implementing features like rank multiplication.
  • Motivation to Combine: A POSITA would combine Kim and Rajan for several reasons. First, they are analogous arts with similar stacked memory structures, making Rajan a natural source for implementation details. Second, a POSITA would be motivated to modify Kim’s package to comply with the well-known JEDEC industry standards, as taught by Rajan, to ensure commercial compatibility. This would involve incorporating Rajan’s teachings on JEDEC-compliant terminals, control signals, and emulation logic into Kim’s control die. Third, a POSITA would be motivated to add more memory chips to Kim’s stack (as Kim suggests is possible) and would look to Rajan for how to manage multiple die groups sharing common data busses.
  • Expectation of Success: Petitioner asserted a high expectation of success, as combining the known JEDEC interface of Rajan with the stacked memory architecture of Kim was a predictable integration of standard components to achieve a known result.

Ground 2: Claims 1-14, 16-19, and 29-34 are obvious over Riho in view of Rajan.

• Prior Art Relied Upon: Riho (Application # 2011/0026293) and Rajan (Patent 8,041,881).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Riho, like the ’060 patent, explicitly taught a stacked memory package designed to reduce electrical load. Riho disclosed a control chip (logic LSI chip) and stacked SDRAM chips organized into distinct groups (e.g., first and second DRAM sets). Critically, Riho taught connecting pairs of SDRAMs to a shared TSV to reduce the data signal load by half. This arrangement directly taught the claimed limitations of a first and second group of array dies connected to separate die interconnects. Rajan was again introduced to provide the motivation for making Riho’s package compatible with JEDEC standards, including adding a JEDEC-compliant interface, external terminals, and emulation logic for features like rank multiplication.
  • Motivation to Combine: The motivation to combine Riho and Rajan was similar to that for Ground 1. A POSITA implementing Riho’s load-reduction technique would be motivated to ensure the resulting memory package could interface with standard host systems. Rajan provided the well-known solution of a JEDEC-compliant buffer chip architecture and control schemes. The combination would predictably yield a JEDEC-compatible, low-load memory package.
  • Expectation of Success: The combination was presented as straightforward, involving the application of standard JEDEC interface solutions (from Rajan) to a specific stacked memory architecture (from Riho).

Ground 3: Claims 1-6, 8-14, 16-19, and 29-34 are obvious over Kim and Rajan, in further view of Wyman.

• Prior Art Relied Upon: Kim (Application # 2011/0103156), Rajan (Patent 8,041,881), and Wyman (Patent 7,969,192).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground built upon the Kim and Rajan combination from Ground 1 and added Wyman to address claim limitations related to driver sizing (e.g., claim 15). Kim’s structure inherently featured signal paths of different lengths, as the TSV to the top slave chip (C2) is longer than the TSV to the lower slave chip (C1). Wyman taught that in such stacked chip arrangements, shorter paths have less load and require less drive, while longer paths have more load and require more drive. Wyman further taught that using a single, full-capacity driver for both paths would be "wasteful" and "overkill." Wyman therefore disclosed using drivers sized appropriately for the load of their respective paths.
  • Motivation to Combine: A POSITA, having combined Kim and Rajan, would be motivated to improve the power efficiency of the design. Recognizing the different path lengths and corresponding loads in Kim’s structure, the POSITA would be motivated by Wyman’s teachings to implement different-sized drivers for the data conduits associated with each TSV. This would optimize performance and reduce power consumption, a well-known goal in memory design.
  • Expectation of Success: Petitioner argued a POSITA would have a reasonable expectation of success in applying Wyman's principle of optimized driver sizing to the known stacked architecture of Kim, as it was a predictable design choice to improve efficiency.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including a combination of Riho and Rajan in further view of Riho2 (Application # 2010/0195364) to teach optimizing drive capacity based on parasitic resistance.

4. Arguments Regarding Discretionary Denial

• §325(d) Arguments: Petitioner argued that discretionary denial under §325(d) was unwarranted because the Examiner never considered the primary references asserted in the petition (Kim, Rajan, Riho, Wyman, Riho2). Although the Examiner considered a different reference by the same inventor as Rajan, the specific teachings and combinations asserted in the petition were never before the USPTO.
• Fintiv Arguments: Petitioner argued that the Fintiv factors favored institution. A parallel district court case existed, but the ’060 patent was only added to that litigation in May 2022, and this petition was filed quickly thereafter in August 2022. Petitioner asserted the litigation was in its very early stages, significant overlap was unlikely, and the merits of the petition were compelling, all weighing against discretionary denial.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-34 of the ’060 patent as unpatentable.