Intel Corp v. 3D Surfaces LLC

1. Case Identification

• Case #: IPR2022-01589
• Patent #: 7,245,299
• Filed: October 1, 2022
• Petitioner(s): Intel Corporation
• Patent Owner(s): 3D Surfaces LLC
• Challenged Claims: 1-4, 9-11, 17-18

2. Patent Overview

• Title: Method and Apparatus for Rendering Bicubic Surfaces
• Brief Description: The ’299 patent describes a graphics processing unit (GPU) for rendering computer graphics. The purported novelty is an "improved architecture" featuring a specific hardware pipeline where a tessellate unit is coupled between a transform unit and a lighting unit to perform real-time tessellation of object surfaces.

3. Grounds for Unpatentability

Ground 1: Obviousness over 501-Pub and Foley - Claims 1-4, 9, 11, and 17 are obvious over 501-Pub in view of Foley.

• Prior Art Relied Upon: 501-Pub (Application # 2002/0033821) and Foley ("Computer Graphics: Principles and Practice," 2nd Ed., 1990).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that 501-Pub, a pre-issuance publication of a parent to the ’299 patent, disclosed a complete software-based process for rendering bicubic surfaces. This process explicitly included the key steps in the claimed order: transforming control points (Step 0), subdividing surfaces into triangles (tessellation, Steps 1-4), and calculating lighting for the resulting vertices (Step 5). While 501-Pub described implementing this process within a "graphics controller," it lacked specific details on the hardware architecture. Foley, a foundational textbook in computer graphics, taught that high-performance graphics systems achieve speed by implementing rendering processes using a physical pipeline of dedicated processors, where each stage of the conceptual pipeline (e.g., transformation, lighting) is mapped to a separate hardware unit.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references to improve performance, a predictable outcome. A POSITA looking to implement the rendering process of 501-Pub would have turned to Foley's well-known teachings on high-performance hardware architecture. Implementing 501-Pub's intrinsically pipelined process steps on dedicated processors as taught by Foley was a known technique to improve a similar device (a graphics controller) in the same way (increased performance and concurrency).
  • Expectation of Success: A POSITA would have had a high expectation of success because using pipelined hardware architectures was a popular and well-understood approach for building high-performance graphics systems since the 1960s, as noted by Foley. The combination yielded the predictable result of improved performance.

Ground 2: Obviousness over 501-Pub, Foley, and Möller - Claims 10 and 18 are obvious over 501-Pub in view of Foley and Möller.

• Prior Art Relied Upon: 501-Pub (Application # 2002/0033821), Foley (a 1990 computer graphics textbook), and Möller ("Real-Time Rendering," 1999).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds upon the combination in Ground 1. Claims 10 and 18 add limitations requiring the use of several different types of geometric primitives (e.g., strips, fans, meshes) composed of surface patches. Petitioner contended that the 501-Pub/Foley combination already taught a graphics utility library (GLU) for implementing drivers that supported various primitives, including strips and meshes. The Möller reference was added to explicitly teach "fan" primitives and to reinforce that using a variety of complex, vertex-sharing primitives (strips, fans, meshes) was an "extremely common way to increase graphics performance" by reducing the amount of data sent to the graphics pipeline.
  • Motivation to Combine: A POSITA would be motivated to incorporate Möller's teachings into the 501-Pub/Foley system to expand the modeling capabilities of the GLU. Adding support for fan primitives, alongside the strips and meshes taught by Foley, would provide more options for efficiently rendering complex objects. This was a standard technique for improving graphics performance, and Möller confirmed that such primitives were widely supported by graphics APIs at the time.
  • Expectation of Success: Success was predictable because fan primitives were known to provide performance benefits similar to other primitives like strips and were already supported by common graphics systems before the patent's priority date. The combination merely involved using known primitives for their intended and well-understood purpose of performance optimization.

4. Key Claim Construction Positions

• Petitioner argued that the terms "transform unit," "tessellate unit," "lighting unit," and "renderer unit" should be construed as means-plus-function terms under 35 U.S.C. §112, ¶6 (pre-AIA).
• Petitioner proposed that the function for each "unit" is the specific action recited in the claims (e.g., "transforming control points") and the corresponding structure is a "dedicated processor in a GPU programmed" to perform that specific function, as described by the algorithms in the specification. This construction is narrower than the Patent Owner's proposed plain-meaning construction and is central to Petitioner's argument that a pipelined architecture of separate, dedicated processors is required.

5. Key Technical Contentions (Beyond Claim Construction)

• Petitioner dedicated a substantial portion of the petition to arguing that the ’299 patent is not entitled to claim priority to the earlier-filed ’501 Patent (from which 501-Pub originates).
• The core contention was that the ’501 patent's specification lacked written description support for the key "improved architecture" claimed in the ’299 patent—specifically, a hardware-based tessellate unit situated between transform and lighting units.
• Petitioner further argued that the Patent Owner was estopped from claiming priority because, during prosecution of the ’299 patent, it successfully traversed an obviousness-type double patenting rejection by unequivocally arguing that the ’501 patent "does not disclose such a tessellation unit" and that the claims represented a "new type of a graphics processing unit."

6. Arguments Regarding Discretionary Denial

• §325(d) (Advanced Bionics): Petitioner argued against discretionary denial because the primary prior art references (Foley and Möller) and the asserted combinations were never presented to or considered by the Examiner during prosecution. The petition's grounds teach the very feature the Examiner found allowable—the specific placement of the tessellate unit.
• §314(a) (Fintiv): Petitioner asserted that the Fintiv factors weighed against denial. The petition presented a compelling unpatentability challenge, and the median time-to-trial in the co-pending district court litigation was such that a final written decision in the inter partes review (IPR) would likely issue around the same time as the trial, favoring institution.

7. Relief Requested

• Petitioner requests institution of an IPR and cancellation of claims 1-4, 9-11, and 17-18 of the ’299 patent as unpatentable.