Intel Corp v. 3D Surfaces LLC

1. Case Identification

• Case #: IPR2022-01591
• Patent #: RE42,534
• Filed: October 1, 2022
• Petitioner(s): Intel Corporation
• Patent Owner(s): 3D Surfaces LLC
• Challenged Claims: 10-20

2. Patent Overview

• Title: Computer Graphics Rendering
• Brief Description: The ’534 patent relates to computer graphics, specifically an apparatus and method for rendering bicubic surfaces. The purported novelty is a graphics processing unit (GPU) architecture comprising a transform unit, a tessellation unit, and a lighting unit arranged in that specific sequential order.

3. Grounds for Unpatentability

Ground 1: Claims 10-20 are obvious over Sfarti in view of Foley

• Prior Art Relied Upon: Sfarti (Application # 2002/0033821, hereafter “501-Pub”) and Foley (James Foley et al., Computer Graphics: Principles and Practice, 2d ed., 1990).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that 501-Pub, which is the pre-issuance publication of the patent from which the ’534 patent claims priority, discloses the core inventive concept: a graphics rendering process that performs transformation, then tessellation, then lighting, in that order. Specifically, 501-Pub’s disclosed algorithm includes Step 0 (transforming control points), Steps 1-4 (subdividing surfaces into triangles, i.e., tessellation), and Step 5 (calculating lighting). Petitioner asserted that this sequence directly maps onto the claimed GPU architecture of a transform unit, followed by a tessellation unit, followed by a lighting unit. Foley, a foundational textbook on computer graphics, was cited to teach the implementation of such conceptual graphics pipelines using a physical pipeline of dedicated hardware processors for each stage to achieve high performance.
  • Motivation to Combine (for §103 grounds): Petitioner contended a person of ordinary skill in the art (POSITA) would be motivated to implement the sequential rendering process of 501-Pub using the high-performance, pipelined hardware architecture taught by Foley. Foley explicitly teaches that using dedicated processing elements for each stage of a graphics pipeline is the standard method for achieving the performance required for modern graphics. Applying Foley’s well-known hardware pipelining technique to implement 501-Pub's software process was described as a predictable combination to improve performance.
  • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success because, as Foley explained, pipelined architectures have been a common and predictable approach to building high-performance graphics systems for decades.

4. Key Claim Construction Positions

• Petitioner argued that the terms “transform unit,” “tessellation unit,” “lighting unit,” and “rendering unit” are means-plus-function terms under 35 U.S.C. §112, ¶6, because the term “unit” does not connote sufficient definite structure.
• For each term, Petitioner proposed a function derived from the claim language (e.g., “transforming graphic objects”) and identified the corresponding structure from the specification as a “dedicated processor in a GPU programmed to” perform the algorithms disclosed for that function (e.g., transforming control points, subdividing patches until a flatness criterion is met).
• This construction was asserted as critical to tethering the claims to the specific operational steps disclosed, which Petitioner then argued were fully taught by the operational steps in 501-Pub.

5. Key Technical Contentions (Beyond Claim Construction)

• Petitioner dedicated a significant portion of its argument to establishing that the challenged claims are not entitled to the priority date of the earlier ’501 patent. This contention is foundational to treating 501-Pub (published in 2002) as prior art to the challenged claims, which claim a priority date no earlier than 2003. The key arguments were:
  • Lack of Written Description: The ’501 patent allegedly lacks written description support for the "improved architecture" having a tessellation unit specifically coupled between a transform and lighting unit. Petitioner argued this was new matter introduced in a later continuation-in-part application.
  • Broken Priority Chain: The intermediate ’299 patent in the priority chain failed to properly make a specific reference to the ’501 patent, thereby breaking the priority chain under 35 U.S.C. §120.
  • Prosecution History Estoppel: During prosecution of the parent ’299 patent, the Patent Owner allegedly overcame an obviousness-type double patenting rejection by arguing that the ’501 patent did not disclose the claimed hardware architecture. Petitioner argued the Patent Owner is therefore estopped from now taking the contrary position that the ’501 patent provides priority support for that same architecture.

6. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial would be inappropriate under both §325(d) and §314(a) (Fintiv).
• Under §325(d): The specific combination of 501-Pub and Foley was not presented to or evaluated by the Examiner during prosecution. While the Examiner considered the ’501 patent for double patenting purposes, it was not applied as prior art against the finally allowed claims, which included amendments that were key to allowance.
• Under §314(a) (Fintiv): Petitioner asserted that the FWD would issue at approximately the same time as the scheduled trial in the parallel district court litigation in the Western District of Texas. Further, Petitioner argued that the petition presents a compelling, meritorious challenge, particularly based on the priority date and estoppel arguments, which weighs heavily against discretionary denial.

7. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 10-20 of Patent RE42,534 as unpatentable.