Apple Inc v. Zentian Ltd

1. Case Identification

• Case #: IPR2023-00034
• Patent #: 7,979,277
• Filed: November 15, 2022
• Petitioner(s): Apple Inc.
• Patent Owner(s): Zentian Limited
• Challenged Claims: 1, 4-5, 7, 9-10, 12, and 14-16

2. Patent Overview

• Title: Speech Recognition Circuit
• Brief Description: The ’277 patent discloses a speech recognition circuit that divides processing into three main stages: an audio front end for generating feature vectors, a calculating circuit for determining the similarity between feature vectors and acoustic models, and a search stage for identifying words. The patent’s purported novelty lies in implementing the front end and search stage on a first processor while offloading the computationally intensive distance calculations to a second processor, with data pipelined between the stages.

3. Grounds for Unpatentability

Ground 1: Claims 1, 5, 7, 12, and 14-16 are obvious over Jiang, Baumgartner, and Brown.

• Prior Art Relied Upon: Jiang (Patent 6,374,219), Baumgartner (Application # 2002/0049582), and Brown (Patent 5,699,456).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Jiang taught a conventional three-stage speech recognition system including a feature extraction module (front end), a tree search engine that calculates likelihood scores (calculating circuit), and identifies words in a lexical tree (search stage). To address the limitation of implementing the calculating circuit on a separate, second processor (claim 1(e)), Petitioner asserted Baumgartner taught a speech recognition architecture using a main processor (first processor) for front-end and search tasks, while offloading computationally intensive distance calculations to a dedicated Speech Label Accelerator (SLA), which constitutes a second processor. To meet the pipelining limitation (claim 1(f)), Petitioner asserted Brown explicitly taught that stages in a speech recognition system can be pipelined to synchronize operations and efficiently process incoming speech frames.
  • Motivation to Combine: A POSITA would combine Jiang's system with Baumgartner's multi-processor architecture to improve performance, a known benefit of offloading computationally intensive tasks like distance calculation. A POSITA would further incorporate Brown's pipelining, a well-known technique, to enhance throughput and efficiency in the resulting multi-processor system, as this would be a simple design choice with predictable advantages.
  • Expectation of Success: Petitioner asserted a POSITA would have a reasonable expectation of success because using dedicated co-processors and pipelining were well-known, feasible techniques in the art for improving speech recognition systems, and the references used similar hardware and functional blocks.

Ground 2: Claim 4 is obvious over Jiang, Baumgartner, and Brown in view of Kazeroonian.

• Prior Art Relied Upon: Jiang, Baumgartner, Brown, and Kazeroonian (WO 99/41684).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on the combination in Ground 1 to address the additional limitations of claim 4, which requires the first processor to support multi-threaded operation and run the search stage and front end as separate threads. Petitioner argued that Kazeroonian taught a processing server where tasks are divided between separate processing threads, even on a single processor, to improve performance and achieve real-time throughput in a pipelined architecture.
  • Motivation to Combine: A POSITA would be motivated to modify the base Jiang-Baumgartner-Brown system with Kazeroonian’s teachings to advantageously improve performance. Implementing the front-end and search stage functionalities on separate threads on the first processor would be an obvious way to manage concurrent tasks efficiently and avoid data loss in a pipelined system.
  • Expectation of Success: Success was reasonably expected because multi-threading was a well-known technique for managing pipelined operations and was within the skillset of a POSITA to implement.

Ground 3: Claims 9-10 are obvious over Jiang, Baumgartner, and Brown in view of Vensko.

• Prior Art Relied Upon: Jiang, Baumgartner, Brown, and Vensko (Patent 4,567,606).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground addresses the limitations of claims 9 and 10, which require the calculating circuit (termed "speech accelerator") to use an interrupt signal to communicate its status to the front end and search stage. Petitioner contended that Vensko taught a speech recognition system using a master processor and multiple template processors (slave processors) that perform distance calculations. Vensko explicitly disclosed using interrupt signals for communication, where the slave processors interrupt the master processor to signal that results are ready for transfer.
  • Motivation to Combine: A POSITA would find it obvious to incorporate Vensko’s interrupt-based signaling into the pipelined, multi-processor Jiang-Baumgartner-Brown system. This would be a routine and efficient method for the second processor (the accelerator) to inform the first processor (running the front end and search stage) that its distance calculation task was complete and that it was ready for the next feature vector, thereby ensuring smooth data flow.
  • Expectation of Success: A POSITA would expect success because interrupt signals were a standard, well-understood, and easily implemented method for coordinating tasks between processors in computer systems at the time.

• Additional Grounds: Petitioner asserted additional obviousness challenges (Grounds 4, 5, and 6) based on combinations that add Smyth (Patent 5,819,222) as an alternative or cumulative reference for teaching a "calculating circuit for calculating distances."

4. Key Claim Construction Positions

• "calculating means for calculating a distance indicating the similarity between a feature vector and a predetermined acoustic state of an acoustic model" (Claim 14): Petitioner argued this term is a means-plus-function limitation under §112, ¶ 6.
  • Proposed Function: "calculating a distance indicating the similarity between a feature vector and a predetermined acoustic state of an acoustic model."
  • Proposed Corresponding Structure: "a processor," based on disclosure in the ’277 patent describing the distance calculation engine and referencing a coprocessor.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not exercise discretionary denial under Fintiv. Petitioner asserted that the co-pending district court litigation was at a very early stage, with final invalidity contentions not due for many months and trial scheduled to begin after the statutory deadline for a Final Written Decision in the IPR. These factors, Petitioner argued, weigh against denial as they indicate minimal overlap of invested resources and a risk of inefficient parallel proceedings.

6. Relief Requested

• Petitioner requests institution of inter partes review and cancellation of claims 1, 4-5, 7, 9-10, 12, and 14-16 of the ’277 patent as unpatentable.