PTAB

IPR2023-00071

Micron Technology Inc v. Katana Silicon Technologies LLC

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Petition
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1. Case Identification

2. Patent Overview

  • Title: Multichip Stacked Semiconductor Device and Manufacturing Method
  • Brief Description: The ’806 patent discloses a method for manufacturing stacked multichip semiconductor modules. The purported invention involves applying an adhesive layer to the entire back surface of a semiconductor wafer before dicing it, creating individual chips with pre-applied adhesive backsides to simplify the vertical stacking process.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ball and Mostafazadeh - Claims 3-5, 20-22, 27-28, and 31 are obvious over Ball in view of Mostafazadeh.

  • Prior Art Relied Upon: Ball (Patent 7,166,495) and Mostafazadeh (International Publication No. WO 1996/13066).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ball taught the core structure of the challenged claims: a stacked multichip module using both flip-chip and wire bond interconnections. Ball disclosed a lower chip flip-chip bonded to a substrate and an upper chip adhered back-to-back on the lower chip and then wire-bonded to the substrate. However, Petitioner contended that Ball did not explicitly teach applying the adhesive at the wafer level before dicing. Mostafazadeh was argued to supply this missing element, as it explicitly taught a method of applying a B-stageable adhesive onto a semiconductor wafer and then dicing it to create individual dies with pre-applied adhesive layers. Petitioner asserted that Mostafazadeh’s method directly addresses the problem of adhesive overflow that the ’806 patent purports to solve.
    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine these references to improve manufacturing efficiency. Ball taught the desirable stacked-chip architecture, while Mostafazadeh taught a well-known, cost-effective method for preparing chips for stacking. A POSITA would have been motivated to replace the chip-by-chip adhesive application implied in Ball with the streamlined wafer-level process from Mostafazadeh to reduce costs and improve yield, especially since Mostafazadeh expressly suggested its method could be used to form multichip modules.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because combining the references involved applying a known wafer-level process (Mostafazadeh) to a known device structure (Ball) without any modification to the final product's architecture.

Ground 2: Obviousness over Ball, Mostafazadeh, and Ahmad - Claims 8, 11, and 29 are obvious over Ball and Mostafazadeh in view of Ahmad.

  • Prior Art Relied Upon: Ball (Patent 7,166,495), Mostafazadeh (WO 1996/13066), and Ahmad (Patent 5,790,384).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground built upon the combination of Ball and Mostafazadeh to address dependent claims requiring features for stacking chips of different sizes. Specifically, claim 8 recites a "support member" for a protruding part of a larger second chip stacked on a smaller first chip. Petitioner argued that while Ball disclosed stacking chips of different sizes, Ahmad explicitly taught using an "interposer" as a support member in exactly this configuration. Ahmad’s interposer provided structural support for the overhang of the larger chip, mitigating mechanical stress. Claim 11, which required the support member to have the same coefficient of thermal expansion as the chip, was also taught by Ahmad to prevent stress and cracking during thermal cycles.
    • Motivation to Combine: Petitioner contended that a POSITA, when implementing the stacked-chip design of Ball, would recognize the mechanical instability of having a larger chip overhang a smaller one without support. Ahmad provided a known solution to this precise problem. A POSITA would therefore have been motivated to incorporate Ahmad’s interposer into the Ball structure to improve the package's reliability and structural integrity.
    • Expectation of Success: The combination was presented as a straightforward integration of a known structural support element (Ahmad's interposer) into a known stacked-chip design (Ball) to solve a predictable mechanical problem.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, arguing that claim 33 was obvious over Ball and Mostafazadeh in view of Tsumura (for specific thermocompression wire bonding techniques) and that claim 21 was obvious over Ball and Mostafazadeh in view of Mita (for adding a light-blocking layer to prevent interference with photosensitive components).

4. Key Claim Construction Positions

  • Petitioner argued that no specific claim constructions were necessary to resolve the invalidity challenges. However, it noted that the term "electrode section" was not standard in the industry but would be understood by a POSITA to mean electrical terminals, such as bond pads, on the substrate’s wiring layer used for wire bonding or flip-chip interconnections. This clarification was provided to aid the Board's understanding of how the prior art met this limitation.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that the Board should not exercise discretionary denial under §314(a) based on Fintiv factors. It asserted that the parallel district court litigation was in a very early stage, as the case had been recently transferred and no scheduling order, discovery, or significant substantive activity had occurred. Petitioner further committed that, if the IPR is instituted, it would not pursue the same invalidity grounds in the district court litigation, aligning with PTAB guidance favoring institution under such circumstances.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 3-5, 8, 11, 20-22, 27-28, 31, and 33 of the ’806 patent as unpatentable under 35 U.S.C. §103.