Micron Technology Inc v. Katana Silicon Technologies LLC

1. Case Identification

• Case #: IPR2023-00073
• Patent #: 6,352,879
• Filed: October 28, 2022
• Petitioner(s): Micron Technology, Inc.
• Patent Owner(s): Katana Silicon Technologies LLC
• Challenged Claims: 1-15

2. Patent Overview

• Title: Method of Manufacturing a Semiconductor Device
• Brief Description: The ’879 patent describes a method for manufacturing multi-chip stacked semiconductor devices. The purported invention involves applying an adhesive layer to the back surface of a semiconductor wafer before dicing it into individual chips, which facilitates easier alignment and vertical stacking.

3. Grounds for Unpatentability

Ground 1: Obviousness of Flip-Chip Method Claim 7 over Ball in view of Mostafazadeh

• Prior Art Relied Upon: Ball (Patent 7,166,495) and Mostafazadeh (WO 1996/13066).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ball taught a stacked die multichip module with a flip-chip mounted lower die and a second die mounted back-to-back on top of the first, using an adhesive layer on the lower die's backside. However, Ball did not specify the method of applying the adhesive. Mostafazadeh was argued to supply this missing element by teaching the specific process of applying adhesive to an entire semiconductor wafer and then dicing it to produce individual chips with pre-applied adhesive backsides. The combination was alleged to teach all limitations of independent claim 7, including forming a wiring layer with metal bumps, mounting a first chip face-down (flip-chip), forming an adhesion layer on a wafer, dicing the wafer to create second chips, mounting a second chip back-to-back on the first, wire-bonding the second chip, and sealing the assembly.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the references to improve the manufacturing efficiency of the stacked module in Ball. Mostafazadeh’s wafer-level adhesive application method was presented as a known, common-sense approach that would simplify the chip-stacking process taught by Ball. Mostafazadeh explicitly suggested its process could be used to form multichip modules.
  • Expectation of Success: A POSITA would have a high expectation of success because both references operated in the same technical field, and the combination involved applying a well-known, efficient manufacturing step (from Mostafazadeh) to a known device structure (from Ball) without requiring any modification to the underlying device.

Ground 2: Obviousness of Wire-Bond Method Claims 1-2, 10-11, and 15 over Ball and Fogal in view of Mostafazadeh

• Prior Art Relied Upon: Ball (Patent 7,166,495), Fogal (Patent 5,323,060), and Mostafazadeh (WO 1996/13066).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addressed claims directed to a wire-bonded, rather than flip-chip, configuration for the lowermost chip. Petitioner asserted that while Ball described both flip-chip and face-up (wire-bond) stacking techniques, its figures primarily depicted flip-chip mounting. Fogal was argued to explicitly teach a wire-bond configuration where the lowermost chip is mounted backside-down on a substrate and connected via wire bonds. The combination of Ball’s general stacked module concepts and Fogal’s specific wire-bond implementation was argued to teach mounting a first chip backside-down on a wiring layer. Mostafazadeh, as in Ground 1, supplied the teaching of applying adhesive at the wafer level before dicing to create the chips used in the stack.
  • Motivation to Combine: A POSITA seeking to create a stacked module with a wire-bonded lower chip, a configuration explicitly mentioned as an option in Ball, would look to a reference like Fogal for a clear example of such a design. Combining these known interconnection techniques was conventional. A POSITA would incorporate Mostafazadeh’s method to streamline the manufacturing process for the chips used in the Ball/Fogal structure for the same reasons of efficiency cited in Ground 1.
  • Expectation of Success: Success was expected because the combination merely integrated two well-known and conventional interconnection techniques (wire-bond and stacked-chip) and utilized a known, efficiency-enhancing manufacturing process. All references were technologically compatible.

Ground 3: Obviousness of Wire-Bond Method Claims 5-6 and 13-14 over Ball and Fogal in view of Mostafazadeh and Ma

• Prior Art Relied Upon: Ball (Patent 7,166,495), Fogal (Patent 5,323,060), Mostafazadeh (WO 1996/13066), and Ma (Patent 6,682,954).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground added Ma to address claims reciting more complex wire-bonding schemes, such as those involving a "dummy pad" for signal pass-through. Ma, a Micron patent, was argued to teach a method for upgrading or remediating semiconductor devices by mounting a "patch die" on top of a primary die. Ma's figures showed multi-level wire-bonding where a signal passes from an upper die, through an intermediate die, to a lower die or substrate. Petitioner argued that in a simpler use case where no signal remediation is needed, a bond pad on the intermediate die would function as a "dummy pad" to simply pass the signal through, as recited in the challenged claims.
  • Motivation to Combine: A POSITA designing a complex multichip module as taught by Ball and Fogal would look to a reference like Ma to implement advanced interconnection schemes, such as upgrading an existing chip or routing signals through intermediate chips. Ma was directed to solving problems in the same type of vertically-stacked packages described in the primary references.
  • Expectation of Success: Ma's methods were technologically compatible with the structures in Ball and Fogal, using the same fundamental stacking and wire-bonding techniques. A POSITA would reasonably expect to successfully apply Ma’s teachings to the modules of Ball/Fogal.

• Additional Grounds: Petitioner asserted additional obviousness challenges over combinations including Tsumura (Patent 4,821,944), which was argued to provide specific, well-known details of thermocompression wire-bonding techniques, such as forming a metal ball on the end of a wire.

4. Key Claim Construction Positions

• Petitioner stated that no formal claim construction was necessary but noted that the term "electrode section" is not common in the industry and appears to be a translation artifact. Petitioner explained that a POSITA would understand "electrode sections" to mean the electrical terminals on the substrate, commonly known as bond pads, to which chips are connected via wire bonds or flip-chip bumps.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) based on Fintiv factors would be inappropriate. Petitioner contended that the parallel district court litigation was in a very early stage, with no scheduling order issued and no discovery having occurred. To further mitigate Fintiv concerns, Petitioner stipulated that it would not pursue in district court the same invalidity grounds raised in the petition, or any grounds that could have reasonably been raised, if the IPR is instituted.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-15 of the ’879 patent as unpatentable under 35 U.S.C. §103.