Micron Technology Inc v. Netlist Inc

1. Case Identification

• Case #: IPR2023-00406
• Patent #: 11,016,918
• Filed: January 6, 2023
• Petitioner(s): Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron Technology Texas LLC
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-30

2. Patent Overview

• Title: Flash-DRAM Hybrid Memory Module
• Brief Description: The ’918 patent describes a memory system that includes both volatile (e.g., DRAM) and non-volatile (e.g., flash) memory subsystems. The system incorporates a controller and a backup power supply to facilitate the transfer of data from the volatile memory to the non-volatile memory in the event of a power failure.

3. Grounds for Unpatentability

Ground 1: Obviousness over Harris and FBDIMM Standards - Claims 1-3, 8, 14-15, and 23 are obvious over Harris in view of the FBDIMM Standards.

• Prior Art Relied Upon: Harris (Application # 2006/0174140) and FBDIMM Standards (JEDEC standards JESD82-20 and JESD205).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Harris taught the core elements of a memory module on a printed circuit board (PCB), including an on-board voltage regulator, SDRAM devices, and a buffer. The combination allegedly met the limitations of independent claim 1 by using Harris’s voltage regulator to provide the four regulated voltages specified by the FBDIMM Standards for the various components on the module, such as the SDRAM (e.g., 1.8V), the buffer (e.g., 1.5V), and termination resistors (e.g., 0.9V). Petitioner asserted it was obvious to use well-known, efficient buck converters to generate these multiple step-down voltages from a higher input voltage supplied to the module.
  • Motivation to Combine: A POSITA would combine these references because Harris explicitly disclosed that its invention was a “fully buffered DIMM” (FBDIMM). This would have directly led a POSITA to consult the contemporaneous JEDEC FBDIMM Standards to determine the specific, standardized voltages required to implement the module and its components, such as the DRAM and buffer.
  • Expectation of Success: A POSITA would have had a high expectation of success, as Harris’s on-board voltage regulator was expressly designed to generate "appropriate local voltage levels," and the FBDIMM Standards simply defined what those industry-standard levels were for the specified components.

Ground 2: Obviousness over Ground 1 combination and Amidi - Claims 1-30 are obvious over Harris in view of the FBDIMM Standards and Amidi.

• Prior Art Relied Upon: Harris (Application # 2006/0174140), FBDIMM Standards, and Amidi (Patent 7,724,604).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the base memory module from Ground 1 and added the teachings of Amidi. Petitioner contended that Amidi taught a "voltage supervisory block" that monitors input power and, upon detecting a disruption, triggers a switch to a battery backup to maintain data in memory. This combination allegedly satisfied the limitations of claims requiring a "voltage monitor circuit" that produces a "trigger signal" (e.g., claims 5 and 16). Amidi’s teachings on undervoltage detection thresholds (e.g., 5% or 10% below nominal) were argued to render obvious the specific percentage-based thresholds recited in claims like 7 and 9.
  • Motivation to Combine: A POSITA would combine Amidi with the Harris/FBDIMM system because Harris recognized the need for power reliability and proposed a "redundant" power source. Amidi provided a known, detailed solution for this exact problem—using a voltage monitor and battery backup on a memory module to ensure data integrity during a power failure. This represented applying a known technique to improve a similar device for its intended purpose.
  • Expectation of Success: The combination was a straightforward application of a known backup power technique to a known memory module, yielding the predictable result of improved power reliability.

Ground 4: Obviousness over Spiers and Amidi - Claims 1-30 are obvious over Spiers in view of Amidi.

• Prior Art Relied Upon: Spiers (Application # 2006/0080515) and Amidi (Patent 7,724,604).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner presented Spiers as an alternative base reference that disclosed a memory module (on a PCI card) with volatile SDRAM, non-volatile NAND flash memory, a processor, and a backup power supply (capacitors). Upon power failure detection, Spiers’s module transferred data from the SDRAM to the flash memory. This combination was argued to teach the core invention. Amidi was used to provide specific implementation details, such as using particular types of DDR SDRAM and the standard voltages required to power them, which were generally described in Spiers.
  • Motivation to Combine: A POSITA implementing Spiers’s system, which taught using SDRAM generally, would have been motivated to consult analogous art like Amidi to find specific details on implementing modern memory modules, including the use of standard DDR SDRAM and the necessary voltage regulation schemes. Amidi provided these well-known, off-the-shelf implementation details.
  • Expectation of Success: A POSITA would have reasonably expected success in applying the specific, standardized voltage and memory types from Amidi to the more general system architecture of Spiers, as it involved combining standardized components in a predictable manner.
• Additional Grounds: Petitioner asserted additional obviousness challenges by adding Hajeck (Patent 6,856,556) to the combinations of Ground 2 and Ground 4. Hajeck was relied upon to explicitly teach the inclusion of overvoltage detection in addition to the undervoltage detection taught by Amidi, thereby strengthening the argument for claims requiring a monitor circuit responsive to voltages "greater than a first threshold."

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial would be unwarranted.
• Under §325(d): The prior art combinations were not previously presented to or evaluated by the USPTO during prosecution. While Spiers was listed in an IDS, it was one of over 100 references and was never substantively discussed by the Examiner.
• Under §314(a) (Fintiv): Petitioner argued the Fintiv factors strongly favor institution. The petition was filed as a motion for joinder to an already-instituted IPR (IPR2022-00996). Therefore, the Final Written Decision deadline in the existing case precedes the trial date in the parallel district court litigation. Petitioner also argued that investment in the co-pending litigation has been minimal.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-30 of Patent 11,016,918 as unpatentable.