PTAB

IPR2023-00510

Dell Technologies Inc v. Greenthread LLC

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device with Graded Dopant Concentrations
  • Brief Description: The ’014 patent discloses a semiconductor device with graded dopant concentrations in its active and well regions. The graded doping is purported to create an electric field that aids the movement of charge carriers away from the active surface regions and towards the substrate.

3. Grounds for Unpatentability

Ground I: Claims 1-9, 13-14, 16-18, 20-21, and 23-28 are obvious over Kawagoe.

  • Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kawagoe, a single reference, teaches all limitations of the challenged claims. Kawagoe’s Figure 23 was shown to disclose a twin-well CMOS device with first and second active regions and adjacent well regions formed on a substrate. Petitioner asserted that Kawagoe’s Figure 17, which corresponds to the device in Figure 23, explicitly illustrates a graded dopant concentration that is "gradually lowered in the depthwise direction." This downward-sloping gradient was argued to meet the limitation of aiding carrier movement, as Kawagoe explains this structure causes electrons to be "attracted to the substrate body," thereby reducing soft errors.
    • Motivation to Combine (for §103 grounds): While this is a single-reference ground, the argument relied on combining teachings from different embodiments within Kawagoe. Petitioner contended a person of ordinary skill in the art (POSITA) would have been motivated to fabricate the twin-well CMOS device of Kawagoe's Embodiment 4 on the uniformly-doped epitaxial substrate of Embodiment 1. The motivation cited was Kawagoe's own explicit teaching that doing so lowers cost while providing benefits like "excellent film quality" and improved device performance and reliability.
    • Expectation of Success: Petitioner asserted a high expectation of success, as the combination involves using disclosed elements from a single patent for their stated purposes, which is a predictable design choice.

Ground II: Claims 1-2, 4-9, 13-18, 20-23, and 25-28 are obvious over Wieczorek in view of Wolf.

  • Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (Silicon Processing for the VLSI Era, a 2000 textbook).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner contended that Wieczorek describes a conventional twin-well CMOS device structure that includes all the claimed active regions and well regions. Wieczorek's Figure 2b was argued to explicitly show a graded dopant profile that is highest at the substrate surface and decreases with depth. This graded concentration was asserted to aid carrier movement deep into the substrate. Because Wieczorek describes its device as conventional but does not specify the substrate type, Petitioner relied on the Wolf textbook. Wolf was cited to confirm that a "uniform, lightly doped p- or n-type substrate" is a common and appropriate choice for the conventional twin-well CMOS devices described by Wieczorek.
    • Motivation to Combine: Petitioner argued that a POSITA, when implementing the conventional CMOS device described in Wieczorek, would have been motivated to consult a standard, well-known textbook like Wolf for details on suitable and conventional substrate materials. The motivation was to complete the design of the conventional device using a standard, known-compatible component to achieve predictable results.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because the combination involves using a standard substrate (taught by Wolf) with a conventional CMOS process (taught by Wieczorek), which was a well-understood and predictable manufacturing method.

  • Additional Grounds: Petitioner asserted additional obviousness challenges (Grounds III and IV) based on Kawagoe in view of Gupta (Patent 6,163,877) and Wieczorek-Wolf in view of Gupta, respectively. These grounds added Gupta primarily to explicitly teach forming a plurality of transistors in the active regions to address a potential claim interpretation requiring more than one transistor.

4. Arguments Regarding Discretionary Denial

  • §314(a) (Fintiv Factors): Petitioner argued against discretionary denial, asserting that the petition presents compelling evidence of unpatentability. It contended that the scheduled trial date in the parallel district court litigation is likely to occur after the statutory deadline for a Final Written Decision (FWD), especially considering the median time-to-trial statistics for the district. Further, petitioner noted that discovery in the parallel case was at an early stage, weighing in favor of institution.
  • §325(d): Petitioner argued that denial under §325(d) is unwarranted because the primary prior art references (Kawagoe, Wolf, and Gupta) were never applied or discussed by the Examiner during prosecution of the ’014 patent. Petitioner further asserted that the arguments presented in the petition are not the same or substantially the same as those considered during prosecution, noting that prior art considered for parent applications was either not prior art to the challenged patent or related to different technologies (e.g., bipolar transistors).

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-9, 13-18, and 20-28 of the ’014 patent as unpatentable under 35 U.S.C. §103.