Intel Corp v. BiTMICRO LLC

1. Case Identification

• Case #: IPR2023-00781
• Patent #: 7,826,243
• Filed: March 31, 2023
• Petitioner(s): Intel Corporation
• Patent Owner(s): BiTMICRO LLC
• Challenged Claims: 1, 2, 11, and 12

2. Patent Overview

• Title: Stacked Module with Active and Passive Ports
• Brief Description: The ’243 patent relates to a multiple chip module (MCM) and package stacking technique using identical single or multichip modules for each layer. The core technology involves using serial chain routes and a control circuit within an end module to manage signal paths, particularly for standardized Joint Test Action Group (JTAG) boundary scan testing.

3. Grounds for Unpatentability

Ground 1: Claims 1, 2, 11, and 12 are obvious over Hosomi in view of Sato.

• Prior Art Relied Upon: Hosomi (Application # 2001/0028114) and Sato (WO 2004/072667).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Hosomi discloses the foundational structure of a stacked module comprising multiple, substantially identical semiconductor devices (SDRAM modules) connected vertically. Sato was argued to supply the remaining limitations by teaching a boundary scan controller for testing stacked chips. Sato’s controller uses JTAG-standard daisy-chain connections (the claimed "first serial chain route"), an output bus (the "second serial chain route"), and a control circuit that enables a routing path in the top-most module to output test data, satisfying the limitations of independent claim 1.
  • Motivation to Combine: Petitioner presented several motivations for the combination. First, Sato expressly teaches incorporating its boundary scan controller into stacked semiconductor chips to test the integrity of their interconnections. Second, a POSITA would recognize that testing vertically stacked modules like those in Hosomi was essential for manufacturing, and boundary scan testing is the preferred method as it avoids physical probes. Third, JTAG was a widely known and standardized testing methodology long before the ’243 patent’s filing date, making its application to Hosomi's known structure a predictable combination of known elements.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because combining a standardized, widely used testing architecture (Sato) with a conventional stacked module structure (Hosomi) involved applying known techniques to a known device to achieve a predictable result—a testable stacked module.

Ground 2: Claims 1, 2, 11, and 12 are obvious over Sung in view of Watanabe.

• Prior Art Relied Upon: Sung (Application # 2003/0178228) and Watanabe (Patent 6,791,193).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Sung describes three-dimensional integrated circuit systems with identical stacked dies and discloses the necessary logical circuitry, including inter-die boundary scan chains and control circuits. Sung’s control logic uses top-die and bottom-die identification to enable or disable routing paths, which maps to the claimed control circuit in an "end module" that responds to a signal from another module. However, Sung provides limited detail on the physical interconnections between modules. Watanabe was asserted to supply this missing element by teaching standard pad-via-ball structures for physically and electrically connecting stacked semiconductor layers.
  • Motivation to Combine: The primary motivation argued was that Sung teaches systems applicable to "stacked multi-chip modules" but lacks implementation details for interconnecting them. A POSITA seeking to build Sung’s system would be motivated to look to references like Watanabe, which is in the same field of 3D packaging and explicitly teaches a well-known method for such interconnections. Furthermore, Sung itself suggests using existing manufacturing technologies like "solder mounds" and "3D via pads," which would directly lead a POSITA to the pad-via-ball structures taught by Watanabe.
  • Expectation of Success: Petitioner contended that a POSITA would expect success in combining a known logical system (Sung) with a standard, well-understood physical interconnection method (Watanabe). The combination was presented as a predictable implementation choice, especially since the ’243 patent itself admits that the underlying module and package-level stacking technologies were pre-existing.

4. Key Claim Construction Positions

• "a plurality of modules each comprising": Petitioner argued this phrase is a limitation within the body of the claim, not part of the preamble. The proposed construction, "each module in the stacked module comprising," would require every individual module in the stack to possess all the subsequently recited features (e.g., active ports, passive ports, serial chain routes), a key element of its invalidity argument.
• "passive port": Petitioner proposed construing this term as "a connection between a passive ball on one surface of a SDRAM module and a passive pad on another surface of the same SDRAM module." This construction is based on a specific definition the patentee added to the specification during prosecution to overcome an indefiniteness rejection, and Petitioner argued this lexicography should control.

5. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §314(a) based on Fintiv factors, noting that the parallel district court litigation is in its very early stages. The trial date is projected for February 2025, more than two months after the statutory deadline for a Final Written Decision (FWD), and no claim construction or significant discovery has occurred.
• Petitioner also argued against denial under §325(d), addressing a prior IPR (IPR2018-01720) on the ’243 patent. Petitioner contended that because it was not a party to the prior IPR, which was terminated by settlement before an FWD, denial is inappropriate. It was further argued that the current petition presents new and different prior art combinations and addresses claim construction issues not previously considered by the Patent Office.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1, 2, 11, and 12 of Patent 7,826,243 as unpatentable.