Intel Corp v. BiTMICRO LLC

1. Case Identification

• Case #: IPR2023-00782
• Patent #: 8,010,740
• Filed: April 1, 2023
• Petitioner(s): Intel Corporation
• Patent Owner(s): Bitmicro LLC
• Challenged Claims: 1, 9-15, 32, and 34

2. Patent Overview

• Title: Optimizing Memory Operations in a Storage Device
• Brief Description: The ’740 patent describes a memory system that uses a mapping table to optimize I/O operations in a solid-state storage device. The table maps host-side Logical Block Addresses (LBAs) to device-side Physical Block Addresses (PBAs), enabling the operational load to be distributed across different memory resources to increase efficiency and reduce latency.

3. Grounds for Unpatentability

Ground 1: Obviousness over Bruce-006 - Claims 1 and 14 are obvious over Bruce-006.

• Prior Art Relied Upon: Bruce-006 (Patent 6,000,006).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Bruce-006 discloses all elements of independent claim 1. Bruce-006 teaches a "unified re-map table" for a flash memory system that maps logical addresses from a host to physical block addresses (PBAs) of flash memory devices. This table is used to perform memory operations, such as wear-leveling swaps, in response to host I/O requests. Petitioner contended that Bruce-006’s "logical-block address (LBA)" corresponds to the ’740 patent’s "LBA set," and that its table entries containing these LBAs are the claimed "logical fields." The PBAs in the table are the claimed "PBA fields." Furthermore, Bruce-006's teachings on interleaving to improve performance by enabling parallel accesses constitute the claimed "optimized memory operations." For claim 14, Petitioner asserted that address bits in Bruce-006’s PBAs used to identify a "device within a bank" or "bank within the system" correspond to the claimed "group identifier."

Ground 2: Obviousness over Bruce-006 and SBC - Claims 1 and 14 are obvious over Bruce-006 in view of SBC.

• Prior Art Relied Upon: Bruce-006 (Patent 6,000,006) and SBC (American National Standard for Information Technology - SCSI-3 Block Commands, 1998).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground asserted that implementing Bruce-006's flash memory system with the industry-standard SCSI protocol taught by SBC would render the claims obvious. SBC discloses READ/WRITE commands that can specify a transfer length for a large number of contiguous logical blocks. Petitioner argued that a single host I/O transaction requesting a data transfer larger than what is mapped in a single row of Bruce-006's re-map table would necessarily require accessing multiple sequential LBA sets. This, in turn, would trigger multiple memory operations, which could be interleaved across different flash devices for performance improvement as taught by Bruce-006, thus meeting the "optimized memory operations" limitation.
  • Motivation to Combine: A POSITA would combine the references to provide a standard, efficient interface for Bruce-006's flash memory system, which is described as a replacement for a SCSI hard disk. Implementing the well-known SBC command set was a predictable and logical step to ensure compatibility and "efficient peer-to-peer operation" between the host and the storage device.
  • Expectation of Success: A POSITA would have a high expectation of success, as the SBC standard was specifically designed for block-based storage devices like the flash memory system disclosed in Bruce-006. No technical barriers would prevent the integration.

Ground 3: Obviousness over Bruce-006 and Bruce-251 - Claims 1, 9-15, 32, and 34 are obvious over Bruce-006 in view of Bruce-251.

• Prior Art Relied Upon: Bruce-006 (Patent 6,000,006) and Bruce-251 (Patent 5,822,251).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Bruce-251, a continuation-in-part of Bruce-006, discloses an expandable flash-disk architecture with features corresponding to the detailed access parameters of the dependent claims. Specifically, Bruce-251 teaches an architecture with dual flash buses, dual flash-specific DMA controllers, and multiple banks of flash memory chips. These elements were argued to directly teach the claimed "bus identifier," "FDE [Flash Device Engine] identifier," and "group identifier" recited in claim 9. The combination of Bruce-006's re-map table with Bruce-251's hardware architecture would result in a system where the PBAs in the table necessarily include these identifiers to address specific memory locations across the distributed system.
  • Motivation to Combine: A POSITA would be motivated to incorporate Bruce-006's efficient, unified re-map table into the expandable, high-performance hardware architecture of Bruce-251 to gain the wear-leveling and performance benefits of the table. Because Bruce-251 is a CIP of Bruce-006 and shares inventors, a POSITA would have naturally looked to Bruce-006 to supply implementation details for the wear-leveling routines mentioned in Bruce-251.
  • Expectation of Success: Success was predictable because the re-map table logic of Bruce-006 is fully compatible with the hardware architecture of Bruce-251. The PBA fields in Bruce-006 already contained bits for identifying devices and banks, making their application to Bruce-251’s buses, DMA controllers, and memory banks straightforward.

• Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 1, 9-15, 32, and 34 based on the combination of Bruce-006, Bruce-251, and SBC, arguing this combination provides an even more complete teaching of the claimed invention.

4. Key Claim Construction Positions

• "LBA": Petitioner noted the patent provides express lexicography, defining "LBA" as "an address that is part of a logical addressing system... used by a host."
• "LBA set": Petitioner relied on the patent's definition of "LBA sets" as groupings of "consecutive LBAs." Petitioner used these constructions to argue that the "logical-block address (LBA)" taught in Bruce-006, which represents a block of consecutive pages, corresponds to the claimed "LBA set."

5. Arguments Regarding Discretionary Denial

• §325(d) (Same or Substantially Same Art/Arguments): Petitioner argued denial under §325(d) is inappropriate because the core prior art references—Bruce-006, Bruce-251, and SBC—were never presented to or considered by the USPTO during the prosecution of the ’740 patent.
• §314(a) (Fintiv Factors): Petitioner argued against discretionary denial under Fintiv, stating the petition presents a compelling unpatentability challenge. Further, the co-pending district court litigation is in its early stages, with no scheduling order, claim construction, or expert discovery completed. The estimated trial date is well after the deadline for a Final Written Decision (FWD) in the IPR.

6. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1, 9-15, 32, and 34 of the ’740 patent as unpatentable.