Intel Corp v. BiTMICRO LLC

1. Case Identification

• Case #: IPR2023-00783
• Patent #: 6,496,939
• Filed: April 1, 2023
• Petitioner(s): Intel Corporation
• Patent Owner(s): Bitmicro LLC
• Challenged Claims: 1-3, 6, 10-12, and 15

2. Patent Overview

• Title: Controlling Data in a Computer System
• Brief Description: The ’939 patent describes a method and system for controlling data in a computer when it loses external power. The system activates a plurality of super capacitors to supply temporary backup power to a computing engine, allowing data to be transferred from volatile to non-volatile memory before the system shuts down.

3. Grounds for Unpatentability

Ground 1: Claims 1-3 and 6 are obvious over Nishida, Harari, and Nakao

• Prior Art Relied Upon: Nishida (Japanese Application Publication No. JPH05-108505), Harari (Patent 5,535,328), and Nakao (Patent 5,929,603).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Nishida taught a computer system with a backup power supply (which could be super capacitors) that activates upon power loss to transfer data from volatile main memory to a non-volatile external recording device. Petitioner contended it would be obvious to use an EEPROM, as taught by Harari, for Nishida’s non-volatile device to gain benefits like lower power consumption and higher reliability. The combination of Nishida and Harari was argued to teach all limitations of claim 1 except for deactivating the super capacitors. Nakao was asserted to supply this missing element, as it taught a circuit for preventing over-discharge of storage elements by detecting when their voltage falls to a predetermined level and then cutting off power to the load.
  • Motivation to Combine: A POSITA would combine Nishida/Harari with Nakao to solve the known problem of over-discharging a backup power supply, which Nishida did not address. Nakao’s over-discharge prevention circuit provided a known technique to improve the reliability and safety of Nishida’s system by ensuring an orderly shutdown before the backup power was fully depleted.
  • Expectation of Success: A POSITA would have an expectation of success because Nakao’s teachings on power supply deactivation were directly applicable to computer systems like Nishida’s. The combination involved implementing a known voltage detection and switching mechanism to solve a predictable problem.

Ground 2: Claims 1-3, 6, 10-12, and 15 are obvious over Nishida, Harari, Ergott, and Pilukaitis

• Prior Art Relied Upon: Nishida, Harari, Ergott (Patent 4,965,828), and Pilukaitis (Patent 5,926,383).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground built upon the Nishida/Harari base system. Ergott was introduced for its teaching of a memory backup system that used an up-converter to charge a backup capacitor to a high voltage and a down-converter to supply power back to the system. This significantly increased the amount of stored backup energy. Pilukaitis was added for its disclosure of an undervoltage lockout circuit that turns off a power converter (like a down-converter) when its input voltage drops below a predetermined threshold, thereby protecting the circuit. Petitioner argued this combination taught the claimed method, including activating super capacitors (Nishida), reconfiguring data (Nishida/Harari), and deactivating the power supply based on a predetermined discharge level (Pilukaitis).
  • Motivation to Combine: A POSITA would combine Ergott with Nishida/Harari to address the problem of insufficient backup power, which Nishida acknowledged could lead to partial data transfer. Ergott’s up/down converters offered a known solution to increase backup time. A POSITA would then add Pilukaitis’s undervoltage lockout circuit to the down-converter from Ergott to prevent component failure and excessive heating at low voltages, a known issue with power converters.
  • Expectation of Success: A POSITA would expect success because implementing up/down converters and undervoltage protection were well-known techniques for improving backup power systems. The combination involved substituting Nishida’s basic charger with Ergott’s more advanced converters and adding a standard protection circuit from Pilukaitis.

• Additional Grounds: Petitioner asserted an additional obviousness challenge based on Nishida, Harari, Ergott, Pilukaitis, and Nakamura (Patent 5,710,931), arguing Nakamura taught using a CPU for power supply control. Petitioner also asserted grounds adding the Supercap Manual to the primary combinations to further support the motivation to use multiple super capacitors in parallel for increased backup time.

4. Key Claim Construction Positions

• "means for activating" (claim 10): Petitioner identified the corresponding structure as an up-converter and a down-converter. This function involves activating the super capacitors to supply power upon loss of external power.
• "means for reconfiguring" (claim 10): Petitioner identified the corresponding structure as volatile memory and non-volatile memory. This function involves the transfer of data between the two memory types, as disclosed in the specification’s "save mode."
• "means for deactivating" (claim 10): Petitioner identified the corresponding structure as a down-converter and other circuit elements like switches or gates. The function is to electrically disconnect the super capacitors from the load when they discharge to a predetermined level.

5. Arguments Regarding Discretionary Denial

• §325(d): Petitioner argued denial is inappropriate because the primary references (Nishida, Harari, Nakao, Pilukaitis, Nakamura, Supercap Manual) were never presented to or considered by the Examiner during prosecution. While Ergott was cited, it was not substantively evaluated or used in a rejection. Petitioner argued the Examiner erred by failing to appreciate Ergott’s teachings on up/down converters, which were absent from the other art considered during prosecution.
• §314(a) (Fintiv): Petitioner contended that the Fintiv factors weigh heavily against discretionary denial. The petition presented a compelling unpatentability challenge. Furthermore, the co-pending district court litigation was in its very early stages, with no scheduling order, claim construction, or expert discovery yet to occur. The projected trial date was well after the deadline for a Final Written Decision in this IPR.

6. Relief Requested

• Petitioner requests the institution of an inter partes review and cancellation of claims 1-3, 6, 10-12, and 15 of Patent 6,496,939 as unpatentable.