Intel Corp v. BiTMICRO LLC

1. Case Identification

• Case #: IPR2023-00787
• Patent #: 10,120,694
• Filed: March 31, 2023
• Petitioner(s): Intel Corporation
• Patent Owner(s): Bitmicro LLC
• Challenged Claims: 1, 5, 6, 9, and 12

2. Patent Overview

• Title: Booting an Embedded System Using a Power-On Reset Sequencer Descriptor
• Brief Description: The ’694 patent describes methods and apparatuses for booting an embedded system. The system uses a specialized data structure, termed a "POR [power-on reset] sequencer descriptor," which contains register information and direct memory access (DMA) controller descriptors to initialize and load the system from non-volatile memory.

3. Grounds for Unpatentability

Ground 1: Claims 1, 5, 6, 9, and 12 are obvious over Post in view of Wilson and Kao.

• Prior Art Relied Upon: Post (Patent 8,799,555), Wilson (Patent 7,861,073), and Kao (Patent 7,490,177).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Post disclosed the foundational embedded system apparatus, including a processor (control circuitry), non-volatile memory (NVM), and RAM. Post taught a boot process where boot data, organized in a linked-list format with metadata pointers, is copied from NVM to RAM and its integrity is verified. Petitioner contended that this linked-list of boot data and metadata in Post constituted the claimed "descriptor." Wilson was argued to supply the teaching of including initial register values ("register information") within the boot data to configure system registers during the boot process, a detail not specified in Post. Kao was asserted to teach using a DMA engine to perform the data transfer from NVM to RAM, offloading this task from the main processor. The combination of Post's boot data structure, modified to include Wilson's register information and transferred using Kao's DMA techniques, allegedly rendered the limitations of the independent claims obvious.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Post with Wilson to solve the known problem of initializing system configuration registers during boot-up, a necessary step for which Post did not provide an explicit mechanism. A POSITA would have been motivated to incorporate Wilson's technique of including register values in the boot data to efficiently prepare the system for operation. Further, a POSITA would combine this with Kao because Kao addressed the well-known goal of improving system performance and reducing processor workload by using a DMA controller for data transfers. Offloading the boot data transfer from the processor, as taught by Kao, was a known technique to improve a system like Post's.
  • Expectation of Success: A POSITA would have a reasonable expectation of success in making the combination. The references described compatible technologies (embedded systems, NVM, DMA, register initialization) and addressed interrelated aspects of a standard boot process. Integrating Wilson's register initialization data into Post's boot data structure and using a standard DMA controller as taught by Kao to transfer it were presented as straightforward modifications for a skilled artisan.

Ground 2: Claims 1, 5, 6, 9, and 12 are obvious over Post in view of Wilson, Kao, and So.

• Prior Art Relied Upon: Post (Patent 8,799,555), Wilson (Patent 7,861,073), Kao (Patent 7,490,177), and So (Patent 7,526,679).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the combination of Post, Wilson, and Kao from Ground 1 and added So to explicitly teach the "reset controller" limitation of claim 1[a]. While Petitioner argued that a reset controller was implicit in Post's disclosure of a "startup or reboot command," So was introduced as an alternative to provide an express teaching. So disclosed a system-on-chip (SoC) for an Internet phone that included a dedicated reset controller block. This controller was described as initializing all other controllers on the SoC in response to a reset signal.
  • Motivation to Combine: The motivation to combine the primary references remained the same as in Ground 1. A POSITA would have been motivated to additionally look to So because Post described a boot process initiated by a reset but was silent on the specific implementation of the controller that generates reset signals. So provided this known implementation detail for an SoC in a similar device (a phone), making it a logical source for a POSITA to consult to complete the design of Post's system. The combination was presented as solving a known problem (providing reset signals) using a known technique (a dedicated reset controller block).
  • Expectation of Success: A POSITA would have an expectation of success because adding a standard reset controller, as taught by So, to the SoC of Post was a conventional design choice. So demonstrated that including such a controller in a similar SoC architecture was well within the skill of an ordinary artisan.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §314(a) based on Fintiv factors would be inappropriate. The petition asserted that the co-pending district court case was in its very early stages, with no scheduling order, claim construction, or significant discovery having occurred. Furthermore, the median time-to-trial in the relevant district court (NDCA) would place the trial date well after the statutory deadline for a Final Written Decision (FWD) in the IPR.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1, 5, 6, 9, and 12 of the ’694 patent as unpatentable.