Apple Inc v. Sonrai Memory Ltd

1. Case Identification

• Case #: IPR2023-00819
• Patent #: 6,874,014
• Filed: April 12, 2023
• Petitioner(s): Apple Inc.
• Patent Owner(s): Sonrai Memory Limited
• Challenged Claims: 1, 3, 5, 7, 11-13, and 15

2. Patent Overview

• Title: Multiprocessing Chip Utilizing Multiple Operating Systems
• Brief Description: The ’014 patent describes a multiprocessing system architecture where multiple processors are mounted on a single semiconductor die. The system is configured to run multiple operating systems simultaneously, with processors capable of executing tasks from these different operating systems.

3. Grounds for Unpatentability

Ground 1: Obviousness over Asano and Joy - Claims 1, 3, 5, 7, 11-13, and 15 are obvious over Asano in view of Joy.

• Prior Art Relied Upon: Asano (Application # 2001/0044817) and Joy (Patent 6,542,991).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Asano taught a multiprocessing computer system capable of running a plurality of operating systems (OSs) simultaneously from a main memory. Asano disclosed allocating processor groups to different OSs. To the extent Asano did not explicitly teach mounting its processors on a single die, Petitioner asserted that Joy supplied this limitation. Joy described a horizontal threaded processor architecture that "combines multiple processors on a single integrated circuit die" to augment execution efficiency and decrease latency. Petitioner contended the combination of Asano’s multi-OS system with Joy’s single-die processor architecture rendered the claims obvious.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Asano's multi-OS system with Joy’s single-die processor implementation to achieve well-understood and predictable benefits. Joy explicitly taught that a single-die configuration reduces communication latency, increases processor speed, and improves power efficiency. These known advantages would have motivated a POSITA to apply Joy's efficient hardware architecture to Asano's software management system.
  • Expectation of Success: Petitioner asserted that combining these known technologies would have been a straightforward application of design principles with a high expectation of success, as it involved implementing a known hardware configuration (single-die multiprocessing) with a known software architecture (multi-OS management).

Ground 2: Obviousness over Asano and Babaian - Claims 1, 3, 5, 7, 11-13, and 15 are obvious over Asano in view of Babaian.

• Prior Art Relied Upon: Asano (Application # 2001/0044817) and Babaian (Patent 7,143,401).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground presented a similar argument to Ground 1, with Babaian substituted for Joy. Petitioner again relied on Asano to teach the foundational multi-processor, multi-OS system. Babaian, like Joy, was cited for its disclosure of mounting multiple processors on a single die. Babaian described a "single chip multiprocessor system" suited for parallel execution that substantially increases performance. This combination, Petitioner argued, taught all limitations of the challenged claims.
  • Motivation to Combine: The motivation to combine Asano with Babaian was rooted in achieving known performance improvements. Babaian taught that a single-chip multiprocessor "substantially increases the performance due to parallel and macro-scheduled execution of a multitude of program streams" and allows for "efficiently synchronized data exchange." A POSITA would have been motivated to apply Babaian's single-chip architecture to Asano's system to gain these benefits and to allow for the flexible assignment of processors to different operating systems, a feature described in Babaian.
  • Expectation of Success: Petitioner argued a POSITA would have had a reasonable expectation of success in combining the teachings. The integration was presented as a predictable pairing of a known hardware architecture with a compatible software system to achieve foreseeable improvements in performance and efficiency.

4. Key Claim Construction Positions

• "simultaneously executing two or more operating systems": Petitioner noted agreement with the Patent Owner in co-pending litigation that this term should be construed as "simultaneously executing two or more independent operating systems."
• "multiple processors are connected to said memory via a bus": Petitioner noted agreement that this phrase in claim 3 should be construed as "multiple processors are connected to said memory via the same bus."
• "processor means" (claim 12): For this means-plus-function term, Petitioner stated the agreed-upon function is "executing a plurality of operating system means" and the corresponding structure is the "chip multiprocessor... having multiple processors... mounted on a single die" as shown in Figures 3 and 4 of the ’014 patent and equivalents.
• "memory means" (claim 12): For this means-plus-function term, Petitioner identified the function as "storing said plurality of operating system means." The corresponding structure was identified from the specification as SRAM/DRAM (on the same or separate chips), magnetic media, or optical media.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under Fintiv would be inappropriate. The petition asserted that the co-pending district court case was in its early stages, making a stay pending IPR likely and efficient. It was argued that the district court's trial date of April 8, 2024, was merely tentative and highly uncertain, whereas the PTAB adheres to a statutory deadline for a Final Written Decision. To further mitigate concerns of parallel proceedings, Petitioner stipulated that, if the IPR is instituted, it will not pursue the same invalidity grounds in the district court action. Finally, Petitioner noted that the prior art references asserted in the petition were never considered during the original prosecution of the ’014 patent.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1, 3, 5, 7, 11-13, and 15 of the ’014 patent as unpatentable under 35 U.S.C. §103.