Samsung Electronics Co Ltd v. Netlist Inc

1. Case Identification

• Case #: IPR2023-00847
• Patent #: 10,268,608
• Filed: April 27, 2023
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-12

2. Patent Overview

• Title: Memory Module with Data Buffering Circuits
• Brief Description: The ’608 patent discloses a memory module comprising memory devices, a module control device, and data buffer circuits arranged in a "fly-by" topology. The technology purports to solve signal timing discrepancies by having each data buffer determine a time interval during a write operation, which is then used to adjust signal timing during subsequent read operations to compensate for propagation delays.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hiraishi and Butt - Claims 1-12 are obvious over Hiraishi in view of Butt.

• Prior Art Relied Upon: Hiraishi (Application # 2010/0312956) and Butt (Application # 2007/0008791).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Hiraishi discloses the core architecture of the ’608 patent, including a memory module with a central module control device (command/address/control register buffer), memory devices (chips), and a plurality of data buffer circuits arranged in a fly-by configuration. Hiraishi’s data buffers perform read and write leveling to adjust timing. Petitioner contended that while Hiraishi discloses the necessary components, Butt further teaches the details of implementing a "data path" within such buffer circuits, where strobe signals sample data signals that are then buffered in FIFOs. The combination of Hiraishi's architecture with Butt's data path implementation allegedly discloses all limitations of claim 1, including the tristate buffer and delay circuit controlled by a command processing circuit.
  • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would combine Butt's data path techniques with Hiraishi's memory module to optimize the performance of Hiraishi’s data register buffer. Both references are analogous art addressing the problem of accurate data transmission timing in memory transactions. A POSITA would have been motivated to use Butt's teachings on data sampling and buffering to improve the functionality of Hiraishi’s existing leveling circuits.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because combining the known data path buffering techniques of Butt into Hiraishi's memory module architecture was a straightforward application of known design principles to achieve a predictable result of improved timing control.

Ground 2: Obviousness over Hiraishi, Butt, and Tokuhiro - Claims 1-12 are obvious over the combination of Ground 1 in further view of Tokuhiro.

• Prior Art Relied Upon: Hiraishi (Application # 2010/0312956), Butt (Application # 2007/0008791), and Tokuhiro (Patent 8,020,022).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground was presented to address an interpretation of the claims where the "second memory operation" (a read) is delayed by an amount determined during a "first memory operation" (a write). Petitioner argued that Hiraishi's read and write leveling operations are independent. Tokuhiro, however, explicitly teaches calculating read delays based on delays determined during write operations to compensate for fly-by delays, especially those larger than one clock cycle. Therefore, adding Tokuhiro's teachings to the Hiraishi/Butt combination provides the specific limitation of using write-timing to control read-timing.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Tokuhiro with Hiraishi to simplify Hiraishi’s independent read-leveling circuitry, making it more efficient. Tokuhiro's technique of setting read delays based on write delays is an elegant solution to the same fly-by delay problem Hiraishi addresses. A POSITA would be motivated to adopt this more efficient method to reduce circuit complexity and the time required for leveling operations.
  • Expectation of Success (for §103 grounds): Success would be expected because implementing Tokuhiro's delay calculation method in Hiraishi's data buffers is a predictable integration of known timing compensation techniques. The combination would result in a memory system with a simplified and more efficient read leveling operation.

• Additional Grounds: Petitioner asserted additional obviousness challenges for specific dependent claims. Grounds 3 and 5 added Ellsberry (Application # 2006/0277355) to teach the use of 4-bit wide memory devices (for claims 5, 8, and 12). Ground 4 added Kim (Patent 6,184,701) to teach a metastability detection circuit (for claims 6-8).

4. Key Claim Construction Positions

• Petitioner argued that while no formal construction is necessary, the grounds for unpatentability hold under both a narrow construction and the broader interpretations allegedly advanced by the Patent Owner in related litigation.
• "memory operations": Petitioner noted that Patent Owner has broadly interpreted this to include not just normal reads/writes but also initial read/write leveling operations.
• "delay...determined by the command processing circuit": Petitioner argued that Patent Owner has interpreted this to include programming of delays by a system memory controller, whereas the patent specification suggests the determination is made within the buffer circuit itself. Petitioner asserted its grounds are valid under either interpretation.

5. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §314(a) and §325(d).
• Fintiv Factors (§314(a)): Petitioner contended that denial is inappropriate because the IPR petition was filed quickly, before the ’608 patent was formally added to co-pending district court litigation against Samsung. Further, a related litigation between Micron and Netlist is stayed, with no trial date set.
• Advanced Bionics Factors (§325(d)): Petitioner asserted that denial is unwarranted because the primary prior art references (Hiraishi, Butt, Tokuhiro, Kim) and the specific combinations argued were not considered during the original prosecution of the ’608 patent. While a related reference (Ellsberry) was in an IDS, it was one of hundreds and never substantively reviewed by the Examiner.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-12 of the ’608 patent as unpatentable under 35 U.S.C. §103.