PTAB

IPR2023-01230

Western Digital Technologies Inc v. Longitude Licensing Ltd

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1. Case Identification

2. Patent Overview

  • Title: Supply Voltage Generating Circuit
  • Brief Description: The ’701 patent discloses a method and semiconductor device for generating a supply voltage. The circuit selects one of two available input power supply voltages and, based on that selection, changes the number of active booster stages in a charge pump circuit to generate a desired boosted output voltage.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zhang and Javanifard - Claims 1-18 are obvious over Zhang in view of Javanifard.

  • Prior Art Relied Upon: Zhang (Patent 7,427,888) and Javanifard (Patent 5,767,735).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Zhang taught the core concept of selecting between two input power supplies of different voltages (a lower VCC and a higher VPP) to feed a charge pump circuit. However, Zhang’s charge pump had a fixed number of stages. Petitioner asserted that Javanifard addressed the known disadvantages of fixed-stage pumps by teaching a charge pump with a variable number of booster stages, configurable via switches. Javanifard taught that the number of active stages could be varied to accommodate different input voltage levels while achieving a desired output level. The combination of Zhang’s selectable dual-voltage input with Javanifard’s configurable, variable-stage booster circuitry allegedly rendered the limitations of independent claims 1 and 10 obvious. For example, when Zhang’s lower voltage input is selected, Javanifard’s teachings would call for using a higher number of booster stages, and when the higher voltage input is selected, a lower number of stages would be used, directly mapping to the challenged claims.
    • Motivation to Combine: A POSITA would combine Zhang and Javanifard to improve the performance and flexibility of Zhang’s multi-power-source system. Javanifard explicitly taught that its variable-stage design provides benefits such as accommodating different input levels, improving efficiency, and reducing circuit area compared to fixed-stage designs. Applying these known benefits to Zhang’s system was presented as a predictable design choice.
    • Expectation of Success: Petitioner contended there was a high expectation of success, as the combination involved applying a known improvement (variable-stage charge pumps from Javanifard) to a known circuit architecture (dual-input charge pumps from Zhang) to achieve the predictable result of a more efficient and flexible power supply circuit.

Ground 2: Obviousness over Javanifard - Claims 1-18 are obvious over Javanifard.

  • Prior Art Relied Upon: Javanifard (Patent 5,767,735).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was based on the obviousness of combining different embodiments disclosed within Javanifard itself. Petitioner argued that Javanifard’s Embodiment 2 taught a multi-power-source system that selects from multiple input power sources (e.g., VCC and VPP) to supply a charge pump. Javanifard’s Embodiments 1 and 3 separately taught a variable-stage charge pump where the number of active stages can be reconfigured using switches.
    • Motivation to Combine: Petitioner asserted that a POSITA would be motivated to combine these teachings from a single reference to achieve one of Javanifard’s stated goals: creating a charge pump that can accommodate a given output level for different charge pump power supply input levels. Applying the multi-source input from Embodiment 2 to the variable-stage pump of Embodiment 1 or 3 was argued to be an obvious implementation of the patent’s own teachings to create a complete, functional system.

Ground 3: Obviousness with Kang - Claims 9 and 18 are obvious over Zhang, Javanifard, and Kang or Javanifard and Kang.

  • Prior Art Relied Upon: Zhang (Patent 7,427,888), Javanifard (Patent 5,767,735), and Kang (“Charge Pump Circuits with Low Area and High Power Efficiency for Memory Applications,” a 2006 journal article).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground specifically addressed claims 9 and 18, which required the booster circuitry to comprise capacitors formed using "thin gate oxide transistors." Petitioner argued that the base combination of Zhang and Javanifard (or Javanifard alone) taught all other elements of the claims. Kang was introduced because it explicitly taught using thin-oxide MOSFETs as pumping capacitors in charge pump circuits.
    • Motivation to Combine: The motivation to add Kang’s teaching was to reduce the overall circuit area, a primary and constant objective in semiconductor design. Kang expressly stated that using thin-oxide capacitors "can reduce the area of charge pumps greatly while keeping their driving capability." A POSITA designing the charge pump of the primary combination would have found it obvious to implement the pumping capacitors with Kang’s well-known, area-saving thin-oxide transistor design.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be improper. It asserted that the parallel district court litigation involving the ’701 patent was in its very early stages, with no trial date or claim construction schedule set.
  • A motion to stay the relevant portion of the district court case had been granted, mitigating concerns of inefficiency and duplicative efforts.
  • Petitioner also stipulated that, if the IPR is instituted, it would not pursue the same grounds or prior art in the parallel litigation.
  • Under the Advanced Bionics test, Petitioner argued institution was favored because the primary prior art references (Zhang, Javanifard, and Kang) were not considered by the USPTO during the original prosecution of the ’701 patent.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-18 of the ’701 patent as unpatentable.