PTAB

IPR2023-01242

Semiconductor Components Industries LLC v. Greenthread LLC

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1. Case Identification

2. Patent Overview

  • Title: VLSI Semiconductor Device
  • Brief Description: The ’222 patent describes a very-large-scale integration (VLSI) semiconductor device featuring a substrate with distinct active regions for forming transistors. The core invention relates to creating a graded dopant concentration in portions of these active regions or adjacent well regions to aid the movement of charge carriers away from the device surface and towards the substrate, purportedly to improve device performance and reliability.

3. Grounds for Unpatentability

Ground 1: Claims 1-14, 16-21, and 23-42 are obvious over Kawagoe

  • Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kawagoe, a single reference, discloses or renders obvious all limitations of the challenged claims. Kawagoe teaches a CMOS integrated circuit device built on a p-type epitaxial substrate, which includes a first active region with an nMOS transistor and a second active region with a pMOS transistor. Critically, Kawagoe explicitly teaches that the impurity concentrations in its p-wells and n-wells are "gradually lowered in the depthwise direction from the principal surface." Petitioner asserted this downward-sloping graded concentration inherently creates an electric field that aids carrier movement away from the surface and toward the substrate body to reduce soft errors caused by alpha particles, directly mapping to the central limitation of the challenged claims.
    • Motivation to Combine (for §103 grounds): As a single-reference ground, the motivation was to apply known semiconductor design principles disclosed within Kawagoe. For certain dependent claims, Petitioner argued a person of ordinary skill in the art (POSITA) would have been motivated to use a uniformly-doped epitaxial substrate (an option in Kawagoe) instead of a latchup-resistant one to achieve "excellent film quality," lower defect densities, and reduced manufacturing cost, as taught by Kawagoe.
    • Expectation of Success (for §103 grounds): Petitioner contended a POSITA would have had a reasonable expectation of success because Kawagoe describes in detail the fabrication and function of CMOS devices with graded wells, explaining that the structure reduces soft errors—the same purpose articulated in the ’222 patent.

Ground 2: Claims 1-2, 4-9, 13-23, 25-28, and 32-42 are obvious over Wieczorek in view of Wolf

  • Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (Silicon Processing for the VLSI Era, 2000).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Wieczorek describes a conventional prior-art twin-well CMOS device with n-channel and p-channel transistors in separate wells. Wieczorek's figures illustrate that the dopant concentration in the wells is highest at the surface and decreases with depth, creating the claimed graded concentration. Petitioner further argued that, based on admissions made during the prosecution of a parent patent, this known downward-sloping gradient was understood in the art to create a "built-in" electric field that sweeps carriers deep into the substrate, thereby aiding carrier movement as claimed.
    • Motivation to Combine (for §103 grounds): A POSITA reading Wieczorek's disclosure of a conventional CMOS device on an "appropriate substrate" would have been motivated to consult a standard textbook like Wolf for details on suitable substrates. Wolf confirms that a uniform, lightly doped p-type or n-type bulk wafer was a common and cost-effective choice for such twin-well CMOS devices. The combination was presented as applying a known fabrication process (Wieczorek) to a known, suitable starting material (taught by Wolf) to achieve a predictable result.
    • Expectation of Success (for §103 grounds): Success was expected because the combination involved applying well-understood, conventional CMOS manufacturing techniques to a standard, compatible substrate to create a standard CMOS device, a process with well-known and predictable outcomes.

  • Additional Grounds: Petitioner asserted four additional grounds that mirror the core arguments of Grounds 1 and 2.

    • Grounds 3 and 4 added Gupta (Patent 6,163,877) to the Kawagoe and Wieczorek-Wolf combinations, respectively. Gupta was used to explicitly teach forming a plurality of transistors in each active region using techniques like chaining and diffusion sharing to achieve the high packing density required for VLSI devices.
    • Grounds 5 and 6 added Silverbrook (Patent 6,614,560) to the Kawagoe and Wieczorek-Wolf combinations, respectively. Silverbrook, which discloses a CMOS image sensor, was used to provide the motivation and technical basis for implementing the fundamental CMOS device structures of Kawagoe or Wieczorek-Wolf in an image sensor, as required by claims 19 and 37.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv, asserting the merits of the petition are exceptionally strong, particularly the single-reference obviousness ground based on Kawagoe. It was also argued that the trial in the parallel district court case is not scheduled and, based on median time-to-trial statistics for the District of Delaware, would not occur until long after a Final Written Decision (FWD) in this IPR.
  • Petitioner also argued against denial under §325(d), stating that the primary prior art references (Kawagoe, Wolf, Gupta, Silverbrook) were never cited, applied, or discussed by the Examiner during the prosecution of the ’222 patent. The arguments presented in the petition were therefore not the same or substantially the same as those previously considered by the USPTO.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-9, 13-28, and 32-42 of the ’222 patent as unpatentable.