Semiconductor Components Industries LLC v. Greenthread LLC

1. Case Identification

• Case #: IPR2023-01243
• Patent #: 10,510,842
• Filed: July 27, 2023
• Petitioner(s): Semiconductor Components Industries, LLC
• Patent Owner(s): Greenthread LLC
• Challenged Claims: 1-18

2. Patent Overview

• Title: Semiconductor Device with Graded Dopant Concentration
• Brief Description: The ’842 patent discloses a semiconductor device featuring active regions with a graded dopant concentration. This gradient is purported to create an electric field that aids the movement of charge carriers from a first surface toward a second surface of the substrate.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kawagoe - Claims 1-2, 4-10, and 12-18 are obvious over Kawagoe.

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kawagoe, which teaches a twin-well CMOS device, discloses all limitations of the challenged claims. Kawagoe describes forming nMOS and pMOS transistors in separate active regions on a substrate. Crucially, Kawagoe teaches that the well regions (which contain the transistor channels) have a graded dopant concentration that gradually decreases with depth, moving from the principal surface toward the substrate body. Petitioner asserted this downward-sloping gradient inherently "aids carrier movement" by attracting unwanted charge carriers (generated by alpha-particle strikes) away from the active regions and into the substrate, a known method for reducing soft errors.
  • Motivation to Combine: While a single-reference ground, the argument relied on combining teachings from different embodiments within Kawagoe. Petitioner contended a POSITA would find it obvious to fabricate the twin-well device of Kawagoe's Embodiment 4 on the uniformly-doped epitaxial substrate of Embodiment 1. This was presented as a simple substitution of one known substrate type for another, both described in Kawagoe, to achieve predictable benefits such as lower manufacturing cost, improved film quality, and higher production yield.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because Kawagoe details the use of both uniformly-doped and latchup-resistant substrates for forming its CMOS devices, repeatedly emphasizing their suitability and similarity.

Ground 2: Obviousness over Wieczorek and Wolf - Claims 1-3, 5-11, and 13-18 are obvious over Wieczorek in view of Wolf.

• Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (Silicon Processing for the VLSI Era, a 2000 textbook).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner asserted that Wieczorek describes a conventional twin-well CMOS device with all the core claimed features except for the specific substrate type. Wieczorek explicitly discloses first and second active regions containing n-channel and p-channel transistors, respectively. It also illustrates that the channel regions have a graded dopant concentration that is highest at the surface and decreases with depth. Petitioner argued this structure meets the limitation of aiding carrier movement toward the substrate, relying on admissions made during prosecution of a parent patent for the same physical phenomenon. Wolf, a standard textbook, was used to supply the missing substrate limitation.
  • Motivation to Combine: A POSITA, when reviewing Wieczorek's description of a conventional CMOS device on an unspecified "appropriate substrate," would naturally consult a standard, authoritative textbook like Wolf for further details. Wolf was cited to confirm that a "uniform, lightly doped p- or n-type substrate" is a suitable and common choice for the twin-well CMOS devices taught by Wieczorek. The combination was framed as simply applying well-known, foundational knowledge from Wolf to complete the conventional teachings of Wieczorek.
  • Expectation of Success: Success would be highly predictable, as the combination involves using a standard substrate (taught by Wolf) with a standard CMOS device structure (taught by Wieczorek) according to established manufacturing principles.

• Additional Grounds: Petitioner asserted additional obviousness challenges (Grounds III and IV) by combining Gupta (Patent 6,163,877) with the references of Grounds I and II, respectively. Gupta was introduced to explicitly teach forming a plurality of transistors in each active region to minimize chip area, addressing a potential claim interpretation requiring multiple devices.

4. Key Technical Contentions (Beyond Claim Construction)

• A central technical contention was that the claimed function of "aiding carrier movement" via a graded dopant concentration was a well-understood physical phenomenon in the prior art. Petitioner argued that during prosecution of a parent patent, the applicant admitted that a downward-sloping dopant concentration was known to create a "built-in" unidirectional electric field that sweeps carriers deep into the substrate. This admission, supported by prior art like Jastrzebski (Patent 4,481,522), was used to show that the functionality described in the ’842 patent was not novel or non-obvious over prior art structures (like those in Kawagoe and Wieczorek) that possessed the same graded doping profile.

5. Arguments Regarding Discretionary Denial

• Petitioner argued extensively that the Board should not exercise its discretion to deny institution.
• Against Fintiv Denial (§314(a)): Petitioner contended that the grounds presented compelling evidence of unpatentability, particularly the single-reference obviousness ground based on Kawagoe. It was also noted that none of the cited references were before the Examiner during prosecution. Furthermore, a trial in the parallel District of Delaware litigation was not yet scheduled and would likely occur well after a Final Written Decision (FWD) in the IPR, and that district has a history of granting stays pending IPR outcomes.
• Against §325(d) Denial: Petitioner argued that the prior art and arguments are not the same or substantially the same as those considered during prosecution. The primary reference from prosecution (Hong) was argued to not be prior art, and the newly cited references (Kawagoe, Wieczorek, Wolf, Gupta) were neither applied nor discussed by the Examiner. The art was asserted to be non-cumulative, addressing claim limitations in a manner the Examiner did not have an opportunity to consider.

6. Relief Requested

• Petitioner requests institution of IPR and cancellation of claims 1-18 of Patent 10,510,842 as unpatentable.