Mercedes Benz USA LLC v. Daedalus Prime LLC

1. Case Identification

• Case #: IPR2023-01333
• Patent #: 10,049,080
• Filed: August 18, 2023
• Petitioner(s): Mercedes-Benz USA, LLC
• Patent Owner(s): Daedalus Prime LLC
• Challenged Claims: 1-24

2. Patent Overview

• Title: Power Management in a Multi-Core Processor
• Brief Description: The ’080 patent discloses a multi-core processor with a power management system that utilizes two distinct pluralities of cores: a first plurality of high-performance, high-power cores and a second plurality of lower-performance, power-efficient cores, both supporting the same instruction set. The system is designed to save power by disabling the high-power cores when computational demand drops below a certain threshold, while keeping the power-efficient cores active.

3. Grounds for Unpatentability

Ground 1: Obviousness over Sutardja - Claims 1-4, 7-12, 15-20, and 23-24 are obvious over Sutardja.

• Prior Art Relied Upon: Sutardja (Application # 2008/0288748, incorporating by reference Application # 2007/0083785).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Sutardja taught a multi-core processor with high-power (HP) and low-power (LP) cores that support the same instruction set, with power differences arising from transistor gate size. Sutardja’s system disabled the HP cores when "system load" dropped below a predetermined point, while the LP cores remained active. Petitioner asserted that a core profile module within the operating system monitored this demand and triggered a hardware-based core switching module to control the transition. While Sutardja explicitly disclosed a plurality of HP cores, Petitioner argued a POSITA would find it obvious to use a plurality of LP cores to handle concurrent low-power applications without needing to activate the power-hungry HP cores. This modification was allegedly supported by the incorporated Sutardja ’785 application, which disclosed multiple low-power secondary processors (CPU and GPU).
  • Motivation to Combine (for §103 grounds): A POSITA would be motivated to implement multiple LP cores in Sutardja’s system to enhance power efficiency, a primary goal of the reference. This would prevent the system from needing to activate an HP core when the processing capacity of a single LP core was exceeded by multiple low-intensity tasks, thereby achieving greater power savings.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success in using multiple LP cores, as this was a known design choice for servers and Sutardja already contemplated using multiple HP cores for scalability.

Ground 2: Obviousness over Sutardja in view of Rychlik - Claims 5-6, 13-14, and 21-22 are obvious over Sutardja in view of Rychlik.

• Prior Art Relied Upon: Sutardja (Application # 2008/0288748) and Rychlik (Application # 2011/0145615).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addressed dependent claims requiring the stepwise disabling of additional LP cores as demand continues to fall below subsequent lower thresholds, until only one core remains. Petitioner contended that Sutardja provided the base multi-core system with pluralities of HP and LP cores. Rychlik was cited for its express teaching of this precise power management strategy: disabling cores one-by-one in response to a continued drop in workload below a "next lower threshold." Rychlik also taught lowering the operating frequency or voltage of the last remaining core as demand drops further.
  • Motivation to Combine (for §103 grounds): A POSITA implementing Sutardja's system with multiple LP cores would combine it with Rychlik's teachings to further optimize power consumption. Rychlik provided a known, granular method to avoid "wasting power" during periods of very low demand, directly aligning with Sutardja’s objective.
  • Expectation of Success (for §103 grounds): The combination involved applying a known power-saving technique from Rychlik to a similar multi-core system in Sutardja to achieve the predictable benefit of enhanced power efficiency.

Ground 3: Obviousness over Mathieson in view of Sutardja - Claims 1-4, 7-12, 15-20, and 23-24 are obvious over Mathieson in view of Sutardja.

• Prior Art Relied Upon: Mathieson (Application # 2011/0213950) and Sutardja (Application # 2008/0288748).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner presented Mathieson as an alternative primary reference that disclosed a multi-core processor with a first set of "fast" cores and a second set of "slow" cores having different power profiles due to using faster, higher-leakage transistors in the fast cores. Mathieson taught disabling the fast cores when workload dropped below a threshold. Petitioner argued that while Mathieson disclosed that the core sets implemented "substantially the same functionality," it did not explicitly require the same instruction set. Sutardja was introduced to supply this limitation, as it expressly taught that its HP and LP cores may use the "same as or a subset of the" instruction set to achieve "dynamic compatibility" and allow for seamless switching between core types.
  • Motivation to Combine (for §103 grounds): A POSITA implementing Mathieson's processor would combine its teachings with Sutardja to find a concrete method for achieving the "same functionality." Sutardja’s use of a common instruction set provided a direct and well-understood solution for enabling the efficient state transfers between different core types that Mathieson described.
  • Expectation of Success (for §103 grounds): Success would be expected because the combination merely integrated a specific, known technique (Sutardja's common instruction set) into a highly similar system (Mathieson's) to achieve the predictable result of dynamic compatibility.
• Additional Grounds: Petitioner asserted additional obviousness challenges based on Sutardja in view of Carmack (Application # 2009/0309243) and Mathieson/Sutardja in view of Rychlik but relied on similar design modification theories.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) was improper. It contended that under the USPTO's Fintiv guidance, a parallel International Trade Commission (ITC) proceeding is not a basis for denial.
• Petitioner also argued against denial under §325(d), asserting that its grounds were not based on the same art or arguments previously considered by the examiner. Specifically, Petitioner claimed that key references like Mathieson, Carmack, and Rychlik were never presented during prosecution. Furthermore, it argued the examiner committed a material error by failing to consider the teachings of the Sutardja ’785 application, which was incorporated by reference into the cited Sutardja ’748 application and allegedly disclosed the plurality of low-power cores that the applicant had argued was missing from the prior art.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-24 of the ’080 patent as unpatentable.