Mercedes Benz USA LLC v. Daedalus Prime LLC

1. Case Identification

• Case #: IPR2023-01343
• Patent #: 8,898,494
• Filed: August 23, 2023
• Petitioner(s): Mercedes-Benz USA, LLC
• Patent Owner(s): Daedalus Prime LLC
• Challenged Claims: 1-7, 13-15, 17-18

2. Patent Overview

• Title: Efficiently balancing performance and power in an integrated circuit.
• Brief Description: The ’494 patent discloses a method for dynamically managing power within an integrated circuit by balancing performance and power allocation between processing cores (e.g., CPU, GPU) and a communication bus, based on measured workloads and a predefined power limit for the circuit.

3. Grounds for Unpatentability

Ground 1: Obviousness over Bose - Claim 1 is obvious over Bose.

• Prior Art Relied Upon: Bose (Patent 7,421,601).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Bose discloses all limitations of claim 1. Bose describes a multi-core integrated circuit with a power/performance monitoring and control unit (PMCU) system that manages power distribution among various components to maximize performance within a given power envelope, which corresponds to the claimed thermal dissipation capacity. Petitioner asserted that Bose’s “interconnect 108” is the claimed communication bus, its processor “cores 112” are the claimed cores, and its local PMCUs (e.g., 116, 118-1) function as the claimed bus and core workload monitors. The global PMCU 110 acts as the claimed “balancing control,” receiving workload data from the local PMCUs and dynamically tuning power allocation between the cores and the interconnect based on a system-wide power budget. Bose also teaches reducing power consumption while maintaining operation above a low limit through techniques like clock gating, rather than powering components off.
  • Motivation to Combine (for §103 grounds): Not applicable (presented as anticipation or, in the alternative, obviousness).
  • Expectation of Success (for §103 grounds): Not applicable.

Ground 2: Obviousness over Bose, White, and Simeral - Claims 3, 14-15 are obvious over Bose in view of White and Simeral.

• Prior Art Relied Upon: Bose (Patent 7,421,601), White (Patent 7,263,457), and Simeral (Application # 2009/0150689).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addresses dependent claim 3, which recites specific power management actions: increasing bus frequency and capping core frequency when bus workload exceeds a threshold. Petitioner contended that while Bose provides the base system for dynamic power management, White and Simeral explicitly teach these frequency adjustment techniques. White discloses increasing the frequency of a common bridge logic (the bus) when it becomes a performance bottleneck while reducing frequencies of individual logic cores to reduce overall power consumption. Simeral teaches a data path controller that monitors bus activity level and, if it exceeds a threshold, adjusts component frequencies (increasing the busy component, decreasing others) to meet performance objectives under a power limit.
  • Motivation to Combine (for §103 grounds): A POSITA would combine these references to enhance the power management capabilities of the Bose system. Since the Bose interconnect could become a performance bottleneck—a known issue in multi-core systems—a POSITA would look to known solutions like those in White and Simeral to manage bus and core frequencies dynamically to alleviate the bottleneck and improve overall performance.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because the references address the same technical problem (power management in multi-core ICs) with compatible solutions. Integrating the frequency adjustment logic of White and Simeral into Bose’s PMCU framework was presented as a straightforward application of known principles.

Ground 3: Obviousness over White - Claims 4 and 7 are obvious over White.

• Prior Art Relied Upon: White (Patent 7,263,457).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground targets independent claim 4, a non-transitory storage medium claim reciting energy efficiency operations. Petitioner argued that White’s power management logic 200, which can be implemented in software, performs the claimed steps. White discloses a multi-core integrated circuit with logic cores (processing elements) and a common bridge logic (communication bus). Its power management logic monitors component workloads (by monitoring operating voltages/frequencies) within a power limit, which White explicitly states can be a thermal design power limit (as recited in claim 7). Petitioner asserted it would be obvious for White's system to determine if a processing element is a bottleneck (as it already does for the bus) and, in response, cap the frequencies of other components while determining if the bus can accommodate the workload, as these are routine considerations in dynamic power management.
  • Motivation to Combine (for §103 grounds): Presented as a single-reference obviousness ground. The motivation was to apply White’s disclosed bottleneck-mitigation techniques, explicitly taught for the communication bus, to the processor cores in a predictable manner to optimize overall system performance.
  • Expectation of Success (for §103 grounds): A POSITA would expect success because applying the same power/frequency adjustment logic to a different but analogous component (a core instead of a bus) was a predictable design choice.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including claims 2 and 13 over Bose in view of Anderson and Naffziger; claims 5-6 and 17-18 over White in view of Anderson and Naffziger; and claims 1, 3, 14-15 over White in view of Simeral. These grounds relied on similar principles, adding references like Anderson to teach heterogeneous (CPU/GPU) cores and ring interconnects, and Naffziger to teach frequency adjustments in producer-consumer thread scenarios.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under Fintiv is unwarranted because Petitioner has been dismissed from all parallel district court and ITC litigation concerning the ’494 patent, meaning no parallel proceeding exists that will decide the patentability issues raised in the petition.
• Petitioner further argued that denial under General Plastic is inappropriate. This is Petitioner’s first IPR against the ’494 patent, and Petitioner has no relationship with the petitioners in a separate IPR (IPR2023-00617). The petition also asserted different grounds and challenges claims not at issue in the other IPR. Finally, Petitioner argued against denial under §325(d) because the primary references (Bose and White) and the asserted combinations were not considered during the original examination.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-7, 13-15, and 17-18 of the ’494 patent as unpatentable.