Innoscience Zhuhai Technology Co Ltd v. Efficient Power Conversion Corp

1. Case Identification

• Case #: IPR2023-01382
• Patent #: 9,748,347
• Filed: September 20, 2023
• Petitioner(s): Innoscience (Zhuhai) Technology Company, Ltd., and Innoscience America, Inc.
• Patent Owner(s): Efficient Power Conversion Corporation
• Challenged Claims: 1-3

2. Patent Overview

• Title: Method for Manufacturing Enhancement-Mode GaN Transistor
• Brief Description: The ’347 patent discloses a method for manufacturing an enhancement-mode gallium nitride (GaN) high electron mobility transistor (HEMT). The method involves creating a stacked gate structure with a p-type gate material and an overlying gate metal, where the purported novelty lies in etching the gate metal to form a pair of horizontal “ledges” on the surface of the p-type material to reduce gate leakage.

3. Grounds for Unpatentability

Ground 1: Obviousness over Saxler, Beach, and Shenoy - Claims 1-3 are obvious over Saxler in view of Beach and Shenoy.

• Prior Art Relied Upon: Saxler (Application # US 2006/0108606), Beach (Application # US 2007/0007547), and Shenoy (a 1996 journal article).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Saxler taught a method of making a GaN HEMT that includes every feature recited in the claims, specifically in its non-recessed gate embodiments. Saxler disclosed a stacked gate structure with a p-type GaN cap layer and an overlying gate contact, which inherently form both sloped sidewalls and horizontal ledges where the gate contact is narrower than the cap layer.
  • Motivation to Combine: Petitioner contended that Saxler’s method used multiple masking steps. A POSITA would combine Saxler’s device structure with Beach’s self-aligned, single-photomask technique to simplify manufacturing, improve layer alignment, and reduce costs. The POSITA would further incorporate Shenoy’s well-known and conventional isotropic etching technique to controllably undercut the gate metal below the single photomask, predictably creating the symmetric ledges seen in Saxler’s structure.
  • Expectation of Success: The combination represented a simple substitution of known, interchangeable manufacturing techniques (self-alignment from Beach, isotropic etching from Shenoy) into Saxler's process to achieve the predictable result of a more efficiently produced device with improved symmetry.

Ground 2: Obviousness over Saxler and Ahn - Claims 1-3 are obvious over Saxler in view of Ahn.

• Prior Art Relied Upon: Saxler (Application # US 2006/0108606) and Ahn (Patent 5,905,274).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground asserted that to the extent Saxler did not explicitly teach a self-aligned etching process, Ahn supplied the missing teachings. Ahn disclosed using a single photomask with a combination of isotropic and anisotropic etching to create a stacked gate structure with both sloped sidewalls and horizontal ledges, analogous to the structure in Saxler.
  • Motivation to Combine: A POSITA would combine Saxler’s transistor design with Ahn’s single-mask fabrication method to improve alignment and reduce manufacturing costs and complexity compared to Saxler’s implicit two-mask process. Ahn explicitly taught using differential etch rates to make a top gate layer narrower than an underlying layer to form ledges, a technique a POSITA would find obvious to apply to Saxler’s metallic gate contact and p-type semiconductor cap layer.
  • Expectation of Success: Ahn’s methods were described as “preferred” for creating symmetrically aligned layers. A POSITA would have reasonably expected success in applying Ahn’s flexible and well-understood etching techniques to Saxler’s device to achieve the same stepped gate structure more efficiently.

Ground 3: Obviousness over Yoshida, Saxler, Beach, and Shenoy - Claims 1-3 are obvious over Yoshida in view of Saxler, Beach, and Shenoy.

• Prior Art Relied Upon: Yoshida (Japanese Publication No. JP H11-261053), Saxler (Application # US 2006/0108606), Beach (Application # US 2007/0007547), and Shenoy (a 1996 journal article).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Yoshida served as a primary reference, disclosing the fundamental arrangement of a GaN HEMT with a stacked gate and horizontal ledges, but with vertical sidewalls. Saxler provided the key missing element: forming sloped sidewalls on the p-type gate material, a feature the ’347 patent admitted was a conventional technique for reducing gate leakage.
  • Motivation to Combine: A POSITA would have been motivated to modify Yoshida’s transistor by substituting its vertical sidewalls with the sloped sidewalls from Saxler to address the known problem of gate leakage. This represented a simple substitution of one known element for another to gain a predictable improvement. A POSITA would then employ the efficient, single-mask self-alignment and isotropic etching techniques from Beach and Shenoy to fabricate the combined Yoshida-Saxler structure for the same reasons of cost and precision as in Ground 1.
  • Expectation of Success: The combination would predictably result in a transistor with Yoshida’s core structure but with the enhanced performance (lower leakage) afforded by Saxler’s known sloped sidewall geometry.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on the combinations of Saxler, Yoshida, Beach, and Shenoy (Ground 2) and Yoshida and Ahn (Ground 5), which relied on similar design choice and process substitution rationales.

4. Key Claim Construction Positions

• For the claim term “forming side surfaces of the p-type gate material that extend horizontally... and contact the barrier layer,” Petitioner proposed the construction: “forming side surfaces of the p-type gate material such that the bottom of the p-type gate material is more than 10% wider than the top...”.
• Petitioner argued this construction was necessary to capture the element's purpose of reducing gate leakage, as explicitly taught in the ’347 patent’s parent application (Lidow). Petitioner also maintained that the challenged claims were obvious under both its proposed construction and the Patent Owner’s broader construction.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under Fintiv is improper. It cited USPTO interim guidance stating that Fintiv does not apply to parallel ITC proceedings. Further, it noted that the co-pending district court case is stayed, weighing against denial.
• Petitioner also contended that denial under 35 U.S.C. §325(d) is unwarranted because the prior art references asserted in the petition were not before the Examiner during prosecution and are not cumulative to the art of record.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-3 of Patent 9,748,347 as unpatentable.