Cirrus Logic Inc v. Greenthread LLC

1. Case Identification

• Case #: IPR2024-00001
• Patent #: 10,734,481
• Filed: October 12, 2023
• Petitioner(s): Cirrus Logic, Inc.; Omnivision Technologies, Inc.; and AMS Sensors USA Inc.
• Patent Owner(s): Greenthread, LLC
• Challenged Claims: 1-9, 12-27, 30-36

2. Patent Overview

• Title: Semiconductor Device with Graded Dopant Concentrations
• Brief Description: The ’481 patent is directed to a semiconductor device featuring graded dopant concentrations within its active and well regions. This graded doping is purported to create an electric field that aids the movement of charge carriers from the device surface toward the substrate, which can improve device performance by mitigating soft errors.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kawagoe - Claims 1-9, 12-14, 16-27, and 30-36 are obvious over Kawagoe.

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kawagoe, which describes twin-well CMOS devices, discloses all elements of the challenged claims. Specifically, Kawagoe teaches fabricating CMOS devices on an epitaxial substrate with well regions having impurity concentrations that are "gradually lowered in the depthwise direction." Petitioner asserted this graded dopant profile aids carrier movement by creating a concentration gradient that attracts and sweeps unwanted carriers (generated by alpha particles) into the substrate body, thereby reducing soft errors and meeting the core limitations of the independent claims.
  • Motivation to Combine: This is a single-reference ground. However, Petitioner argued a person of ordinary skill in the art (POSITA) would have been motivated to combine features from different embodiments within Kawagoe. A POSITA would have combined the uniformly-doped epitaxial substrate of Kawagoe's Embodiment 1 with the twin-well device structure of Embodiment 4 to reduce manufacturing costs and improve film quality, accepting a predictable trade-off in latch-up resistance.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success because Kawagoe details the use of both uniformly-doped and latch-up resistant substrates for forming similar CMOS devices and repeatedly emphasizes their compatibility.
  • Key Aspects: Petitioner noted that during prosecution of a parent patent, the applicant admitted that a downward-sloping graded dopant concentration was known to create an inherent "built-in" electric field that sweeps carriers into the substrate.

Ground 2: Obviousness over Wieczorek and Wolf - Claims 1-2, 4-9, 12-22, 24-27, and 30-36 are obvious over Wieczorek in view of Wolf.

• Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (a 2000 textbook, Silicon Processing for the VLSI Era).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Wieczorek describes a conventional prior-art twin-well CMOS device that includes all the structural elements of the claims, including active regions and well regions. Wieczorek's figures depict a dopant profile that is highest at the device surface and decreases with depth, thus teaching the claimed graded dopant concentration. Wolf, a well-known semiconductor textbook, was used to supplement Wieczorek’s disclosure by providing background knowledge on conventional CMOS devices, such as confirming the common use of a uniform, lightly doped substrate.
  • Motivation to Combine: A POSITA reading Wieczorek’s description of a conventional CMOS device on an "appropriate substrate" would have been motivated to consult a standard textbook like Wolf for further details on suitable, well-known substrate options. Wolf confirms that a uniform, lightly doped substrate is a common and appropriate choice for the twin-well structure Wieczorek describes.
  • Expectation of Success: The combination would have yielded predictable results, as Wolf merely provides standard, foundational knowledge that fills in conventional details not explicitly specified in Wieczorek. This confirms the operability of the device using known, common manufacturing choices.

Ground 3: Obviousness over Kawagoe/Wieczorek-Wolf and Gupta - Certain claims requiring a plurality of transistors are obvious over the combinations of Ground 1 or Ground 2 in further view of Gupta.

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114), Wieczorek (Application # 2003/0183856), Wolf (a 2000 textbook), and Gupta (Patent 6,163,877).
• Core Argument for this Ground:
  • Prior Art Mapping: These grounds incorporated the analyses from Grounds 1 and 2, adding Gupta to explicitly teach the benefit of forming multiple transistors within a single active region. Gupta is directed to CMOS circuit layout and teaches that a primary goal in chip development is to minimize area by packing a maximum number of transistors into an active region using techniques like "diffusion abutment" and "chaining."
  • Motivation to Combine: A POSITA would combine Gupta’s well-known, area-saving layout techniques with the CMOS fabrication processes of Kawagoe or Wieczorek-Wolf to achieve the recognized and highly desirable goal of high packing density in a semiconductor chip. This combination also gains the soft-error immunity benefit from the graded wells taught by Kawagoe or Wieczorek.
  • Expectation of Success: Success was predictable because Gupta’s layout optimization techniques are process-agnostic and designed to be applied to any standard CMOS fabrication process, such as those described in Kawagoe and Wieczorek-Wolf.
• Additional Grounds: Petitioner asserted additional obviousness challenges (Grounds V and VI) against claims 19 and 36, which recite an "image sensor." These grounds combined Kawagoe or Wieczorek-Wolf with Silverbrook (Patent 6,614,560), which discloses a CMOS image sensor and teaches the incorporation of vendor-supplied CMOS logic cores.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not exercise its discretion to deny institution under either 35 U.S.C. §314(a) (Fintiv) or §325(d).
• Fintiv Factors: Petitioner asserted that the merits of the petition are strong, noting Ground 1 is a single-reference obviousness challenge using art not considered during prosecution. Further, it argued that the district court trial dates in parallel litigation are scheduled near or after the statutory deadline for a Final Written Decision (FWD) in the IPR, and that median time-to-trial statistics suggest the trials will not precede the FWD.
• §325(d) Factors: Petitioner argued that denial under §325(d) is inappropriate because the primary references (Kawagoe, Wieczorek, Wolf, Gupta, and Silverbrook) were never cited or substantively considered by the examiner during prosecution of the ’481 patent. The arguments presented are therefore not the same as, or cumulative to, arguments previously considered by the Patent Office.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-9, 12-27, and 30-36 of the ’481 patent as unpatentable.