Cirrus Logic, Inc. v. Greenthread, LLC

1. Case Identification

• Case #: IPR2024-00001
• Patent #: 10,734,481
• Filed: October 12, 2023
• Petitioner(s): Cirrus Logic, Inc.; Omnivision Technologies, Inc.; and AMS Sensors USA Inc.
• Patent Owner(s): Greenthread, LLC
• Challenged Claims: 1-9, 12-27, and 30-36

2. Patent Overview

• Title: Semiconductor Device with Graded Dopant Concentrations
• Brief Description: The ’481 patent is directed to a semiconductor device having graded dopant concentrations in its active and well regions. This graded doping is purported to aid carrier movement from a first surface of the substrate to a second surface of the substrate.

3. Grounds for Unpatentability

Ground 1: Claims 1-9, 12-14, 16-27, and 30-36 are obvious over Kawagoe.

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114)
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kawagoe, which was not considered during prosecution, discloses all elements of the challenged claims. Kawagoe teaches fabricating twin-well CMOS devices on an epitaxial substrate. It explicitly describes forming wells with impurity concentrations that are "gradually lowered in the depthwise direction" (i.e., a graded dopant concentration). This concentration gradient is disclosed to reduce soft errors by attracting unwanted carriers (electrons) generated by alpha-ray strikes "to the substrate body," thereby aiding carrier movement from the device surface towards the substrate, as claimed.
  • Motivation to Combine (for §103 grounds): This is a single-reference ground. However, Petitioner argued that a person of ordinary skill in the art (POSITA) would be motivated to combine different embodiments within Kawagoe. Specifically, a POSITA would find it obvious to use the uniformly-doped epitaxial substrate of Kawagoe’s Embodiment 1 with the twin-well device of Embodiment 4 to achieve predictable benefits like lower manufacturing cost and improved film quality, as taught by Kawagoe itself.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because Kawagoe details the use of both uniformly-doped and latchup-resistant substrates for forming similar CMOS devices, making the substitution straightforward and the results predictable.

Ground 2: Claims 1-2, 4-9, 12-22, 24-27, and 30-36 are obvious over Wieczorek in view of Wolf.

• Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (a 2000 textbook, Silicon Processing for the VLSI Era)

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner asserted that Wieczorek describes a conventional prior-art twin-well CMOS device having active regions, well regions, and transistors. Wieczorek explicitly shows a dopant profile that is highest at the substrate surface and decreases with depth, thus disclosing a graded dopant concentration in both the channel and well regions. Wolf, a foundational textbook, was used to supplement Wieczorek’s disclosure, confirming that conventional twin-well CMOS devices were commonly formed on uniform, lightly doped substrates. Petitioner argued that the downward-sloping graded dopant concentration taught by Wieczorek was known to create a "built-in" electric field that sweeps carriers deep into the substrate, thus aiding carrier movement as claimed.
  • Motivation to Combine (for §103 grounds): A POSITA, when reviewing Wieczorek’s description of a conventional CMOS device on an "appropriate substrate," would be motivated to consult a standard textbook like Wolf for details on suitable substrate types. Wolf confirms that a uniform, lightly doped substrate is a common and appropriate choice for the twin-well process described by Wieczorek.
  • Expectation of Success (for §103 grounds): Success would be expected because the combination involves applying fundamental, well-understood CMOS manufacturing principles (from Wolf) to a conventional CMOS device structure (from Wieczorek) to achieve predictable results.

• Additional Grounds: Petitioner asserted additional obviousness challenges which build upon the core arguments of Grounds 1 and 2.

  • Grounds III and IV added Gupta (Patent 6,163,877) to the combinations of Ground I and Ground II, respectively. Gupta was cited for its teaching of forming multiple transistors in a single active region to minimize chip area, thereby rendering obvious claims requiring a plurality of transistors.
  • Grounds V and VI added Silverbrook (Patent 6,614,560) to the combinations of Ground I and Ground II, respectively. Silverbrook, which discloses a CMOS image sensor, was cited to demonstrate the obviousness of implementing the semiconductor designs of Kawagoe or Wieczorek-Wolf in an image sensor, as recited in claims 19 and 36.

4. Key Claim Construction Positions

• Petitioner stated that no claim terms require construction to resolve the Petition.
• It argued the challenged claims are unpatentable under either their plain and ordinary meaning or under the Patent Owner's (PO) proposed constructions from related litigation.
• Petitioner specifically noted that even under the PO's interpretation that "an active region ... within which transistors can be formed" only requires a single transistor, the prior art still renders the claims obvious. The additional ground combining Gupta was included to address any interpretation requiring a plurality of transistors.

5. Arguments Regarding Discretionary Denial

• Petitioner argued strongly against discretionary denial under both §314(a) (Fintiv) and §325(d).
• §314(a) Arguments: Petitioner asserted the merits are compelling, as the grounds rely on prior art not considered by the USPTO. It argued the scheduled trial date in the co-pending Western District of Texas case (February 2025) is likely to occur after the statutory deadline for a Final Written Decision (FWD) in this IPR, especially considering the district's median time-to-trial statistics.
• §325(d) Arguments: Petitioner argued that denial is inappropriate because the primary references (Kawagoe, Wieczorek, Wolf, Gupta, Silverbrook) were never cited or substantively evaluated during the prosecution of the ’481 patent. It contended the new art is not cumulative to any art of record and that the arguments presented are substantially different from those considered by the examiner.
• Other Arguments: Petitioner noted that prior IPRs against the ’481 patent were filed by unrelated parties and terminated before an institution decision, and argued that denying institution would severely prejudice the current Petitioners who are defendants in active district court cases.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-9, 12-27, and 30-36 of the ’481 patent as unpatentable.