PTAB

IPR2024-00073

Vizio Inc v. Polaris PowerLED Technologies LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: LED Driver for Driving LEDs in Parallel
  • Brief Description: The ’148 patent discloses a light-emitting diode (LED) driver designed to mitigate voltage ripple and noise in the power supply. The invention achieves this by driving multiple parallel strings of LEDs with staggered pulse-width modulated (PWM) brightness control signals, ensuring that not all LEDs draw current simultaneously.

3. Grounds for Unpatentability

Ground 1: Anticipation by Thomas - Claims 1, 3, 7, 9-12, 14, 17, 18, and 20-22 are anticipated by Thomas.

  • Prior Art Relied Upon: Thomas (Patent 5,317,307).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Thomas, filed 16 years before the ’148 patent, discloses every limitation of the challenged claims. Thomas teaches an LED driver for "power demand load leveling" that drives multiple parallel groups of LEDs. It explicitly describes a pulse width modulator connected to a delay means, which together function as a PWM brightness control signal generator. This generator creates a primary PWM signal and multiple time-delayed (i.e., staggered) versions of that signal. These staggered signals are then applied to their respective parallel LED paths, causing them to activate sequentially and conduct current out of phase with each other, directly corresponding to the core invention of the ’148 patent.
    • Key Aspects: Thomas’s preferred embodiment for the delay means is a 12-bit shift register with taps at different bit positions (e.g., the 4th, 8th, and 12th cells) to generate the staggered signals, directly anticipating the limitations of claims 7, 9, and 10. The resistors in series with the LEDs in Thomas function as the claimed "current set circuits," anticipating claim 3.

Ground 2: Anticipation by Zane - Claims 1-4, 11, 12, 14, 17, and 22 are anticipated by Zane.

  • Prior Art Relied Upon: Zane ("Digital Architecture for Driving Large LED Arrays with Dynamic Bus Voltage Regulation and Phase Shifted PWM," a 2007 APEC conference paper).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Zane, a publicly accessible conference paper, discloses a digital architecture for driving a scalable number of parallel LED "strings." The system uses a digital phase-shifted PWM (PS-PWM) module to control the switching sequence and duty cycle for each string, explicitly generating staggered PWM signals. These signals control programmable linear current sinks (the "current set circuits") for each parallel path. Waveform diagrams in Zane show the LED strings conducting current at the same duty cycle but out of phase.
    • Key Aspects: Unlike Thomas, Zane explicitly discloses that its voltage source is a "boost converter," which is a step-up voltage regulator, thus anticipating claim 2. Zane’s programmable current sinks are detailed as current regulators comprising a current control transistor and a feedback circuit, anticipating claims 3 and 4.

Ground 3: Obviousness of Recirculating Shift Register - Claims 8 and 19 are obvious over Thomas in view of Tatewaki and the knowledge of a POSITA.

  • Prior Art Relied Upon: Thomas (Patent 5,317,307) and Tatewaki (Patent 6,402,354).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground addresses claims 8 and 19, which add the limitation of a shift register that recirculates bits by connecting an end bit position to a first bit position. While Thomas teaches a shift register, it does not explicitly disclose recirculation. Tatewaki teaches an LED lamp for a car interior that uses a "ring counter" to control brightness. Petitioner argued a person of ordinary skill in the art (POSITA) would understand a ring counter to be a well-known type of recirculating shift register.
    • Motivation to Combine: A POSITA would combine Thomas and Tatewaki to improve Thomas’s driver. By modifying Thomas’s shift register into a ring counter, a specific PWM duty cycle could be set and then continuously recycled without needing the upstream modulator to constantly generate the bit sequence. This modification would be particularly beneficial for applications like the computer indicator lights mentioned in Thomas, where brightness levels are set and then maintained for long periods.
    • Expectation of Success: The modification would have been straightforward, involving a simple connection of the shift register’s output to its input, a well-known technique for which a POSITA would have a high expectation of success.

  • Additional Grounds: Petitioner asserted additional challenges, including that claims 1, 3, 6, 7, 9-12, 14, 17, 18, and 20-22 are obvious over Thomas alone; claims 2, 13, and 15 are obvious over Thomas in view of Applicant-Admitted Prior Art (AAPA) and POSITA knowledge; and claims 1-5, 11-17, and 22 are obvious over Zane alone.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial would be improper under both 35 U.S.C. §325(d) and §314(a).
  • §325(d): The primary references, Thomas and Zane, were never before the Examiner during prosecution. The Examiner allowed the claims based on the reasoning that no prior art taught conducting current through parallel LEDs at the same duty cycle but out of phase—the very feature that Petitioner argued is explicitly taught by both Thomas and Zane.
  • §314(a) (Fintiv Factors): This inter partes review (IPR) is the first filed against the ’148 patent. The parallel district court litigation is in its infancy, with minimal discovery, no depositions, and no trial date set. Furthermore, the presiding judge has a history of granting stays pending IPR outcomes.

5. Relief Requested

  • Petitioner requests institution of an IPR and cancellation of claims 1-22 of the ’148 patent as unpatentable.