Cadence Design Systems Inc v. Semiconductor Design Technologies LLC

1. Case Identification

• Case #: IPR2024-00356
• Patent #: 7,603,636
• Filed: January 5, 2024
• Petitioner(s): Cadence Design Systems, Inc.
• Patent Owner(s): Semiconductor Design Technologies, LLC
• Challenged Claims: 1-3, 7-10, and 13-14

2. Patent Overview

• Title: Assertion Generating System, Circuit Verifying System, and Assertion Generating Method
• Brief Description: The ’636 patent describes systems and methods for automatically generating properties and assertions used to verify integrated circuit (IC) designs. The invention aims to reduce human error by generating these verification elements from a graphical specification, such as a flowchart or timing diagram, which describes the intended functionality of the IC.

3. Grounds for Unpatentability

Ground 1: Obviousness over Abarbanel and Kobayashi - Claims 1-2, 7-9, and 13 are obvious over Abarbanel in view of Kobayashi.

• Prior Art Relied Upon: Abarbanel (a 2000 publication titled "FoCs – Automatic Generation of Simulation Checkers from Formal Specifications") and Kobayashi (Patent 4,922,432).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kobayashi taught a system for graphically editing an IC specification (a flowchart) to automatically generate a list of properties (a "statelist") describing the design's state machine. Abarbanel taught a methodology and tool (“FoCs”) that automatically translated formal properties, expressed in a language like RCTL, into VHDL assertion descriptions (“checkers”) for simulation and verification. The combination allegedly disclosed all limitations of the challenged claims.
  • Motivation to Combine: A POSITA would combine Kobayashi’s intuitive, graphical front-end for creating specifications and properties with Abarbanel’s efficient back-end for automatically generating verification checkers. This combination would address the known inefficiency of manual checker writing, which Abarbanel explicitly sought to improve. Kobayashi's system was ready for improvement because it lacked robust verification after netlist generation, a gap filled by Abarbanel's assertion-based checkers.
  • Expectation of Success: A POSITA would have had a high expectation of success. The combination involved using Kobayashi’s output (a statelist describing a state machine) as input for Abarbanel. This was straightforward because state machine properties were known to be expressible in RCTL, the language used by Abarbanel.

Ground 2: Obviousness over Narain and Kobayashi - Claims 1-2, 7-9, and 13 are obvious over Narain in view of Kobayashi.

• Prior Art Relied Upon: Narain (Patent 6,651,228) and Kobayashi (Patent 4,922,432).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground asserted a similar combination, but substituted Narain for Abarbanel. Kobayashi again provided the graphical front-end for generating properties from a flowchart. Narain taught an "Intent-Driven Verification" architecture that automatically generated assertion descriptions from a "control file" containing the express design intent.
  • Motivation to Combine: A POSITA would have been motivated to use the statelist automatically generated by Kobayashi as the input control file for Narain’s verification system. This would leverage Kobayashi’s user-friendly graphical specification method to feed Narain’s automated assertion generation engine, thereby eliminating errors from manually creating the control file and simplifying the overall design and verification workflow.
  • Expectation of Success: Success was predictable because Kobayashi’s statelist and Narain’s control file served the same purpose: to provide a list of properties expressing design intent. A POSITA could have readily adapted Narain’s control file reader to parse the syntax of Kobayashi’s statelist, as both described state machine properties.

Ground 3: Obviousness over Abarbanel and Feyerabend - Claims 1, 3, 7-8, 10, and 13 are obvious over Abarbanel in view of Feyerabend.

• Prior Art Relied Upon: Abarbanel (a 2000 publication) and Feyerabend (a 1997 publication titled "A Visual Formalism for Real Time Requirement Specifications").
• Core Argument for this Ground:
  • Prior Art Mapping: This ground replaced Kobayashi’s flowchart-based system with Feyerabend’s timing-diagram-based system. Feyerabend taught graphically editing timing waveform diagrams to automatically generate property formulas (in a temporal logic language) that captured real-time design constraints. Abarbanel, as in Ground 1, taught the automatic conversion of such properties into VHDL checkers for verification.
  • Motivation to Combine: A POSITA would combine Feyerabend's graphical editor for timing specifications with Abarbanel's automatic checker generation to create a complete, automated design-and-verify workflow for time-based requirements. Both references aimed to automate tasks previously done manually, and their functionalities were complementary.
  • Expectation of Success: The combination was a simple substitution of one known element for another. A POSITA would have understood that Feyerabend's property formulas could be expressed in RCTL for use with Abarbanel's tool, as both were temporal logic languages suitable for describing timing constraints.
• Additional Grounds: Petitioner asserted additional obviousness challenges (Grounds 4-6) for claim 14 by combining McKeone (Patent 6,957,413), which taught conventional semiconductor manufacturing, with the primary combinations of Grounds 1-3, respectively. The motivation was that after designing and verifying an IC, the natural next step would be to manufacture it using known methods as taught by McKeone.

4. Key Claim Construction Positions

• "graphically editing": Petitioner argued this term meant "editing a visual expression, as opposed to editing text." This construction was central to its argument that prior art methods of editing flowcharts (Kobayashi) and timing diagrams (Feyerabend), which involved manipulating visual elements and their spatial relationships, met the claim limitation. This contrasted with the Patent Owner’s allegedly narrower construction of "editing with a graphical user interface."

5. Key Technical Contentions (Beyond Claim Construction)

• Interchangeability of Property Languages: A central technical contention underpinning multiple grounds was that a POSITA would have found it obvious to substitute one formal property language for another. Petitioner argued that expressing the properties from Kobayashi's "statelist" or Feyerabend's TPTL formulas in the RCTL language required by Abarbanel would have been a simple, predictable substitution, as these were all known temporal logic languages used to describe state machine behavior and timing constraints.

6. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial would be inappropriate.
  • Against Fintiv Denial: The petition asserted that the parallel district court litigation was at a very early stage and was stayed pending a motion to dismiss, with no trial date set, weighing heavily against denial.
  • Against §325(d) Denial: Petitioner contended that none of the primary prior art references (Abarbanel, Kobayashi, Narain, Feyerabend) were cited or considered by the Examiner during the original prosecution of the ’636 patent, meaning the petition raised novel validity questions.

7. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 7-10, and 13-14 of the ’636 patent as unpatentable.