PTAB

IPR2024-00469

Monolithic Power Systems Inc v. Greenthread LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: CMOS Semiconductor Device
  • Brief Description: The ’502 patent discloses a CMOS semiconductor device with layers having a graded dopant concentration. This gradient is intended to create a static electric drift field that sweeps minority carriers from the device's active region at the surface down to its substrate, purportedly improving performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Onoda - Claims 7-8 are obvious over Onoda.

  • Prior Art Relied Upon: Onoda (Japanese Application H8-279598).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Onoda, a single reference, teaches every element of the challenged claims. Onoda discloses a CMOS device with a semiconductor substrate, a surface layer containing an active region (source and drain), and an intermediate epitaxial layer that functions as the claimed "single drift layer." Petitioner asserted that Onoda’s figures and description show this epitaxial layer has a dopant concentration that gradually decreases with depth from the surface to the substrate. This downward-sloping dopant gradient inherently generates a first static, unidirectional electric drift field that aids the movement of minority carriers toward the substrate. Furthermore, Onoda teaches forming well regions (e.g., P-well 105a) within this drift layer, and these wells also possess a graded dopant profile, thereby creating the claimed second static, unidirectional electric drift field.
    • Motivation to Combine (for §103 grounds): As a single-reference ground, Petitioner argued that all claimed features are present in Onoda, making a combination unnecessary.
    • Expectation of Success (for §103 grounds): Not applicable for a single-reference ground.

Ground 2: Obviousness over Onoda in view of Nishizawa - Claims 7-8 are obvious over Onoda in view of Nishizawa.

  • Prior Art Relied Upon: Onoda (Japanese Application H8-279598) and Nishizawa (Patent 5,384,476).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Onoda discloses the core structure of the challenged claims, as detailed in Ground 1. Nishizawa was introduced to explicitly teach and confirm the underlying principles that are inherent in Onoda. Nishizawa describes a CMOS device with a buried region having a graded impurity concentration that is "progressively decreasing toward the p type substrate" to create a "drift electric field." This field is explicitly for drifting minority carriers to the substrate to prevent device errors. Petitioner argued that Nishizawa's express teachings on using graded dopant profiles to create electric fields for minority carrier management would have confirmed to a person of ordinary skill in the art (POSITA) the function and properties of the graded dopant structure disclosed in Onoda.
    • Motivation to Combine (for §103 grounds): A POSITA would combine these references because both are directed to similar CMOS memory devices and address similar problems, such as reducing punch-through. A POSITA would have been motivated to apply Nishizawa’s explicit teachings on generating drift fields with graded dopants to the specific semiconductor structure shown in Onoda to achieve the predictable result of efficient minority carrier removal.
    • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success, as the combination merely applies well-understood principles of semiconductor physics (explicit in Nishizawa) to a compatible device structure (disclosed in Onoda).

Ground 3: Obviousness over Kawagoe - Claims 7-8 are obvious over Kawagoe.

  • Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Kawagoe teaches a CMOS device whose epitaxial layer has an "impurity concentration gradually lowered depthwise." This gradient is explicitly for attracting minority carriers (electrons) to the substrate body to reduce errors, directly matching the purpose of the ’502 patent. Petitioner mapped Kawagoe's disclosure to the claims by identifying its epitaxial layer (2E) as the "surface layer" and "single drift layer," its body (2S) as the "substrate," and its source/drain regions as the "active region." The graded dopant profile in the drift layer creates the first static unidirectional electric field. Kawagoe's p-wells and n-wells, formed within this drift layer, also have graded impurity concentrations and constitute the claimed "well region" generating a second static drift field.
    • Motivation to Combine (for §103 grounds): As a single-reference ground, Petitioner argued that all claimed features are present in Kawagoe, making a combination unnecessary.
    • Expectation of Success (for §103 grounds): Not applicable for a single-reference ground.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under §314(a) (considering Fintiv factors) and §325(d) would be inappropriate.
  • Fintiv / §314(a): Petitioner asserted it presented "compelling evidence of unpatentability" under the Director's Vidal Memo, highlighting the strength of its single-reference obviousness grounds. It noted that none of the asserted prior art references (Onoda, Kawagoe, Nishizawa) were ever examined by the USPTO during prosecution of the ’502 patent.
  • §325(d): Petitioner argued that the Becton Dickinson factors weigh in favor of institution because the grounds are based on art and arguments never before considered by the Office. Petitioner further contended that the asserted art is not cumulative to references that were considered during prosecution, such as Rhodes, because Onoda and Kawagoe describe relevant CMOS memory device features that Rhodes lacked.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 7-8 of Patent 9,190,502 as unpatentable.