PTAB

IPR2024-00476

ARM Ltd v. ICPillar LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: System and method for universal control of electronic devices
  • Brief Description: The ’899 patent relates to a computer-implemented method and system for designing an integrated circuit (IC). The process involves receiving a designer's selection of categorized input and output characteristics for an electronic device, analyzing those selections, and then outputting a hardware IC design and associated software to control the device.

3. Grounds for Unpatentability

Ground 1: Claims 1, 5, 6, 8, and 14 are obvious over Rompaey alone or in combination with CoWare I.

  • Prior Art Relied Upon: Rompaey (Patent 5,870,588) and CoWare I (a 1996 publication titled "CoWare—A design environment for heterogeneous hardware/software systems").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Rompaey, which teaches a hardware/software co-design system called "CoWare," discloses all limitations of the challenged claims. In Rompaey's exemplary design of a "pager" device, a designer selects categorized input characteristics (e.g., a keyboard) and output characteristics (e.g., a display). This selection is received by the CoWare tool, which then analyzes the designer's specifications and library components to generate both a hardware integrated circuit design (in formats like VHDL or a netlist) and the associated software (e.g., device drivers) to control the pager. Petitioner contended this process directly maps to the claimed method of receiving selections, analyzing them, and outputting hardware and software designs. The use of predetermined, reusable components from categorized libraries in Rompaey, such as processor models and "I/O scenarios," was argued to meet the limitations of claims 5 and 6. The CoWare I publication was presented as largely mirroring Rompaey's disclosure and adding further detail, such as explicitly showing "Control Buttons" and a "UART" component for the pager's inputs and outputs.
    • Motivation to Combine: A POSITA would combine Rompaey and CoWare I because the references address the same subject matter, use the same pager design example, share common authors, were published contemporaneously, and the inventors submitted CoWare I to the PTO during the prosecution of Rompaey.
    • Expectation of Success: Given the significant overlap in content and authorship, a POSITA would have had a reasonable expectation of success in combining the teachings of the two references to arrive at the claimed invention.

Ground 2: Claims 1, 5, 6, 8, and 14 are obvious over Banerjee.

  • Prior Art Relied Upon: Banerjee (Application # 2008/0222581).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Banerjee teaches a software tool for designing application-specific integrated circuits (ASICs) and systems-on-a-chip (SoCs) that renders the claims obvious. Banerjee described a designer using a graphical user interface (GUI) to select components from hierarchical categories (e.g., processors, memory, I/O interfaces, graphics) and define their parameters and characteristics for a specific application, such as a "cell phone" or a device for real-time video processing. Petitioner argued this process meets the claim limitation of "receiving a selection of categorized input and output characteristics." The tool in Banerjee then analyzes the selections, performs logic synthesis and optimization, and generates a hardware circuit design (as a netlist or HDL file) and corresponding software (including the operating system and middleware). This was argued to satisfy the "analyzing" and "outputting" steps of the claims. Petitioner further argued that Banerjee's disclosure of using predefined components from libraries and repositories for specific applications, such as a "cellular modem SoC," directly corresponds to the limitations of dependent claims 5 and 6.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that the Board should not deny institution under 35 U.S.C. §325(d) because the Examiner did not consider the asserted prior art references during prosecution, and these references present compelling merits.
  • Petitioner also argued against discretionary denial under Fintiv. It asserted that the parallel district court litigation is in its early stages, with minimal investment and a trial date (March 2025) that is not certain and is expected to occur after a Final Written Decision in this IPR. Petitioner stipulated that it would not pursue invalidity in the district court using the same grounds asserted in the petition, further weighing against denial. Given the strong merits of the petition, Petitioner contended that institution would serve the efficiency and integrity of the patent system.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 5, 6, 8, and 14 of the ’899 patent as unpatentable under 35 U.S.C. §103.