PTAB

IPR2024-00551

Monolithic Power Systems Inc v. Greenthread LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device with Graded Dopant Concentration
  • Brief Description: The ’481 patent is directed to a semiconductor device whose layers have a graded dopant concentration. This gradient creates an electric drift field intended to sweep minority carriers from the active region at the device's surface toward its substrate, purportedly improving upon prior art devices that used uniformly doped regions.

3. Grounds for Unpatentability

Ground I: Obviousness over Kawagoe - Claims 1-9, 13, 15, 17, 20, 22-27, 31-32, and 34 are obvious over Kawagoe.

  • Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kawagoe teaches a semiconductor device with an epitaxial layer where the "impurity concentration gradually lowered depthwise." This gradient is designed to attract minority carriers (electrons produced by alpha rays) to the substrate body to reduce soft errors. Petitioner asserted this structure directly maps to the limitations of independent claims 1 and 20. Specifically, Kawagoe’s p-type substrate with an epitaxial layer, its formation of both n-well and p-well active regions for PMOS and NMOS transistors, and its disclosure of a graded dopant profile within these wells to aid carrier movement were alleged to teach all elements of the challenged claims.

Ground II: Obviousness over Onoda - Claims 1-9, 13, 15, 17, 20, 22-27, 31-32, and 34 are obvious over Onoda.

  • Prior Art Relied Upon: Onoda (Japanese Application H8-279598).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Onoda discloses a nonvolatile semiconductor storage device with a graded dopant concentration to aid downward carrier movement. Onoda’s structure includes a p-type substrate comprising a heavily-doped first semiconductor layer and a lightly-doped second epitaxial layer. Within this structure, multiple p-type and n-type well regions are formed, containing NMOS and PMOS transistors. Petitioner argued that Onoda’s figures depict a dopant concentration that gradually decreases from the top surface through the well regions and toward the substrate. This graded profile, intended to improve latch-up resistance, was asserted to meet the limitations of a graded dopant region that aids carrier movement from the device surface to the substrate, as required by independent claims 1 and 20.

Ground III: Obviousness over Onoda in view of Nishizawa - Claims 1-9, 13, 15, 17, 20, 22-27, 31-32, and 34 are obvious over Onoda in view of Nishizawa.

  • Prior Art Relied Upon: Onoda (Japanese Application H8-279598) and Nishizawa (Patent 5,384,476).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Onoda provides the primary semiconductor device structure, including a layered substrate, multiple active regions in wells, and a downward graded dopant profile. Nishizawa was introduced as teaching the explicit use of such a graded dopant profile to create a "drift electric field" for the express purpose of moving minority carriers from the surface region toward the substrate. Nishizawa explains that this prevents unwanted carriers from flowing into the active circuitry and causing errors, such as "extinction of memory." Petitioner asserted that Nishizawa’s teachings on creating a drift field directly correspond to the function of the graded dopant region claimed in the ’481 patent.
    • Motivation to Combine: A POSITA would combine these references because both address the same fundamental problem in semiconductor devices: controlling unwanted minority carrier movement. Onoda discloses a structure with a graded profile to address latch-up, while Nishizawa explicitly teaches using a graded profile to create a drift field to sweep away such carriers. A POSITA would have looked to Nishizawa's clear teachings to confirm and implement the principles underlying the structure in Onoda to reliably control minority carriers.
    • Expectation of Success: A POSITA would have had a high expectation of success. The combination involved applying Nishizawa’s well-understood principle of using a graded dopant concentration to create a drift field to Onoda’s similar device structure. This amounted to combining known elements to achieve the predictable result of improved minority carrier control.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that the Board should not exercise discretionary denial under 35 U.S.C. §314(a) or §325(d). The petition asserted it presents compelling evidence of unpatentability because the primary references in Grounds II and III (Onoda and Nishizawa) are new and were never examined by the USPTO during prosecution of the ’481 patent.
  • Regarding §325(d), Petitioner argued that its grounds are not cumulative to the art previously considered by the Examiner. It contended that Onoda and Kawagoe describe CMOS memory devices with graded dopants in a manner distinct from the prior art of record (Rhodes), which the Patent Owner had previously distinguished as being directed to a CMOS image sensor.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-9, 13, 15, 17, 20, 22-27, 31-32, and 34 of the ’481 patent as unpatentable.