PTAB

IPR2024-00566

ARM Ltd v. ICPillar LLC

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1. Case Identification

2. Patent Overview

  • Title: Method for Designing an Integrated Circuit
  • Brief Description: The ’657 patent discloses a method and system for designing an integrated circuit (IC) to control an electronic device. The invention allows a developer to select functional parameters (e.g., control, display, input, output) for the device from a hierarchical database, which are then used to automatically generate a hardware IC design and its associated operating software.

3. Grounds for Unpatentability

Ground 1: Obviousness over Banerjee - Claims 1, 5-6, 8-9, and 15-16 are obvious over Banerjee.

  • Prior Art Relied Upon: Banerjee (Application # 2008/0222581).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Banerjee taught a software tool for designing application-specific integrated circuits (ASICs) that rendered the claimed invention obvious. The tool allowed a designer to select components and parameters from hierarchical libraries via a graphical user interface (GUI) to tailor hardware and software for specific applications. Petitioner asserted this process directly mapped to the ’657 patent’s claims. For independent claims 1 and 9, Banerjee’s tool allegedly met the limitations by allowing a user to select values for control, display, input, and output parameters from a hierarchical database (e.g., a "reference library" with selectable "classes" and "subclasses"). The tool then received these selections into memory, analyzed them (by compiling, merging, and optimizing), and outputted both a hardware IC design (in formats like HDL or a netlist) including communication buses, and the corresponding software (OS, drivers, middleware) to control the device.
    • Key Aspects: Petitioner contended that Banerjee’s description of selecting functionality mirrors the language of the ’657 patent, such as defining a system-on-chip (SoC) in terms of its "desired inputs and outputs, as well as desired functionality."

Ground 2: Obviousness over Rompaey alone or with CoWare I - Claims 1, 5-6, 8-9, and 15-16 are obvious over Rompaey in view of CoWare I.

  • Prior Art Relied Upon: Rompaey (Patent 5,870,588) and CoWare I (a 1996 article by Verkest et al.).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Rompaey’s CoWare system, a tool for hardware/software co-design, disclosed the claimed invention. The system allowed a designer to select and refine functional blocks ("models") from hierarchical libraries to generate an IC design and software, using a pager as an exemplary device. Petitioner mapped the limitations of independent claims 1 and 9 by showing that Rompaey’s designer selected parameters from hierarchical libraries containing processor models (for control), I/O scenarios (for input/output), and components for a pager that inherently required a display. The CoWare system’s "co-synthesis" and "SYMPHONY" tools then analyzed these selections to output both the hardware design (e.g., VHDL netlist) with communication buses and the necessary software (e.g., I/O device drivers) to operate the pager. CoWare I was cited to provide additional detail, such as the pager having "Control Buttons."
    • Motivation to Combine: A POSITA would combine Rompaey and CoWare I because the references cover the same subject matter using the same pager example, were authored by the same people, were published contemporaneously, and the inventors submitted CoWare I to the PTO during Rompaey's prosecution.
    • Expectation of Success: Petitioner asserted a high expectation of success in combining the references due to their significant technical overlap, common authorship, and shared prosecution history, indicating they are complementary descriptions of the same system.

4. Arguments Regarding Discretionary Denial

  • Petitioner presented arguments against discretionary denial under 35 U.S.C. §325(d) and §314(a) (Fintiv factors).
  • §325(d): Petitioner argued denial would be improper because the ’657 patent had not been previously challenged in an inter partes review (IPR) and the Examiner did not consider the specific prior art references asserted in the petition.
  • §314(a) (Fintiv): Petitioner argued the Fintiv factors weighed in favor of institution. It asserted that the co-pending district court litigation was in its early stages with minimal investment, and the scheduled trial date (March 2025) was uncertain and likely to occur after a Final Written Decision (FWD) would issue. Furthermore, Petitioner stipulated that it would not pursue invalidity in the district court using the same grounds asserted in the petition, mitigating concerns of overlap and preserving judicial resources.

5. Relief Requested

  • Petitioner requests institution of an IPR and cancellation of claims 1, 5, 6, 8, 9, 15, and 16 of the ’657 patent as unpatentable.