Texas Instruments Inc v. Greenthread LLC

1. Case Identification

• Case #: IPR2024-00672
• Patent #: 10,510,842
• Filed: March 12, 2024
• Petitioner(s): Texas Instruments Incorporated
• Patent Owner(s): Greenthread LLC
• Challenged Claims: 1-18

2. Patent Overview

• Title: Semiconductor Device with Graded Dopant Concentration
• Brief Description: The ’842 patent is directed to a semiconductor device featuring active regions with a graded dopant concentration, which is purported to aid the movement of charge carriers from a first surface toward a second surface of the substrate.

3. Grounds for Unpatentability

Ground 1: Claims 1-2, 4-10, and 12-18 are obvious over Kawagoe

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kawagoe, a single reference, discloses all limitations of the challenged claims. Kawagoe teaches a twin-well CMOS device fabricated on an epitaxial substrate and explicitly discloses that the well regions have a graded dopant concentration that decreases with depth from the principal surface. Petitioner asserted this downward-sloping gradient meets the "graded dopant concentration to aid carrier movement" limitation. Kawagoe explains this structure sweeps unwanted charge carriers (electrons generated by alpha-particle strikes) away from the surface and into the substrate body to reduce soft errors. Petitioner contended that a person of ordinary skill in the art (POSITA) would have found it obvious to form Kawagoe’s device on a uniformly-doped substrate (taught in Kawagoe’s Embodiment 1) instead of the latchup-resistant substrate (taught in Embodiment 4) to improve performance, yield, and cost.
  • Motivation to Combine: As a single-reference ground, the motivation was to combine teachings from different embodiments within Kawagoe. A POSITA would combine the twin-well device of Embodiment 4 with the uniformly-doped substrate of Embodiment 1 for the known benefits of improved film quality, reliability, and lower manufacturing cost, as described by Kawagoe.
  • Expectation of Success: A POSITA would have a high expectation of success, as Kawagoe describes both substrate types as suitable for forming CMOS devices and emphasizes their similarities.

Ground 2: Claims 1-3, 5-11, and 13-18 are obvious over Wieczorek in view of Wolf

• Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (a 2000 textbook, Silicon Processing for the VLSI Era).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Wieczorek describes a conventional twin-well CMOS device with first and second active regions, each containing transistors. Wieczorek explicitly illustrates that the dopant concentration in the well structures is highest at the substrate surface and decreases with depth, thereby disclosing the claimed graded dopant concentration. Petitioner argued this downward-sloping profile inherently aids carrier movement toward the substrate, a known principle of semiconductor physics. Wolf, a standard textbook, was introduced to teach that a uniform, lightly doped p-type or n-type substrate is a common and suitable starting material for the conventional twin-well process described by Wieczorek.
  • Motivation to Combine: A POSITA, when implementing the conventional CMOS device described in Wieczorek on an "appropriate substrate," would be motivated to consult a standard textbook like Wolf. Wolf confirms that a uniform, lightly doped substrate is a standard and suitable choice for such twin-well devices. The combination represents using a known process on a known, suitable starting material.
  • Expectation of Success: Success would be expected and the results predictable, as the combination involves applying a standard fabrication process to a well-known, compatible substrate material.

Ground 3: Claims are obvious over Kawagoe or Wieczorek/Wolf in view of Gupta

• Prior Art Relied Upon: Gupta (Patent 6,163,877) in combination with the references from Grounds 1 and 2.
• Core Argument for this Ground: This ground was presented to address a potential interpretation that the claims require a plurality of transistors or devices within each active region.
  • Prior Art Mapping: Petitioner argued that even if Kawagoe or Wieczorek/Wolf were interpreted to show only a single transistor per active region, adding Gupta renders the claims obvious. Gupta teaches circuit layout techniques for CMOS devices, explaining that a primary goal of chip development is to maximize transistor density by minimizing area. Gupta explicitly teaches techniques like chaining transistors to share diffusion areas, resulting in multiple transistors within a common active region.
  • Motivation to Combine: A POSITA implementing the fabrication processes of Kawagoe or Wieczorek/Wolf would be motivated by the well-known industry goal of high packing density to incorporate the layout optimization techniques taught by Gupta. Applying Gupta’s area-saving layouts to the CMOS structures of the primary references is a straightforward combination of a known layout optimization with a known fabrication process.
  • Expectation of Success: A POSITA would have a high expectation of success because Gupta’s layout techniques are process-agnostic and applicable to any CMOS semiconductor chip, including those fabricated using the methods of Kawagoe or Wieczorek/Wolf.

4. Key Claim Construction Positions

• Petitioner noted that in a prior litigation, the Patent Owner and a third party (Intel) had proposed constructions for several terms.
• Key disputed terms included "active region" and "to aid carrier movement."
• Petitioner asserted that for the purposes of this IPR, no special constructions were necessary and that the challenged claims are unpatentable under any of the previously proposed constructions.

5. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under Fintiv, asserting that the petition presents compelling evidence of unpatentability, as the same grounds have already been instituted in a related IPR proceeding (IPR2023-01243) which Petitioner seeks to join.
• Petitioner stated that the Final Written Decision (FWD) in the joined proceeding is anticipated in February 2025, before the scheduled March 2025 trial date in the parallel district court litigation, weighing in favor of institution.
• Petitioner also argued that denial under §325(d) is unwarranted because the prior art references and arguments presented were not before the Examiner during the original prosecution of the ’842 patent and are not cumulative to the art of record.

6. Relief Requested

• Petitioner requests institution of inter partes review and cancellation of claims 1-18 of Patent 10,510,842 as unpatentable.