PTAB

IPR2024-00721

MediaTek Inc v. MOSAID Technologies Inc

Key Events

Petition

petition Intelligence

Title: LOW LEAKAGE AND DATA RETENTION CIRCUITRY
Brief Description: The ’349 patent relates to reducing power consumption in integrated circuits by mitigating idle power loss from leakage current. The disclosed technique uses sleep transistors and distinct "power islands" in conjunction with an adaptive leakage controller to optimize voltages applied to the power islands when they are in sleep mode.

Prior Art Relied Upon: Takahashi (Application # 2003/0025130).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Takahashi teaches all limitations of the challenged claims. Takahashi discloses an integrated circuit with a logic circuit and an associated switching circuit that functions as a power island with a sleep transistor. It further describes a voltage regulator (claimed "sleep generator") that supplies a variable voltage to the power island, and a control circuit (claimed "adaptive leakage controller") that sends a control signal to the voltage regulator to change the voltage between active and standby modes. Petitioner asserted that a Person of Ordinary Skill in the Art (POSITA) would find it obvious to use a plurality of such power islands, as Takahashi itself describes in other embodiments containing multiple functional circuits (e.g., memories, DSP cores) with individual sleep transistors. Dependent claims relating to state machines and delineating islands by functional IP units were also argued to be disclosed or rendered obvious by Takahashi's teachings on controlling circuit states and its use of distinct functional blocks.
- Motivation to Combine (for §103 grounds): Not applicable (single reference ground).
- Expectation of Success (for §103 grounds): Not applicable (single reference ground).

Prior Art Relied Upon: Takahashi (Application # 2003/0025130), Schutz (Patent 5,440,520).
Core Argument for this Ground:
- Prior Art Mapping: This ground specifically addressed claims 7 and 14, which require the "optimum voltage" to be dependent on both process and temperature variation. Petitioner asserted Takahashi teaches optimizing voltage based on process variations to reduce their effect. Schutz discloses a system for optimizing an integrated circuit's supply voltage based on temperature by using an IC temperature sensor and a device characteristics map.
- Motivation to Combine (for §103 grounds): A POSITA would combine the references to further improve circuit performance and reduce power consumption, as both references address the same problem of providing optimum voltages in integrated circuits. A POSITA would have been motivated to incorporate Schutz’s well-known temperature compensation technique into Takahashi's system to account for temperature variation, a known factor impacting transistor performance that Takahashi did not explicitly address.
- Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success, as the combination involved the straightforward integration of a known temperature sensor into Takahashi's voltage regulation scheme to account for a known variable.

Prior Art Relied Upon: Mizuno (Application # 2003/0102904).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued Mizuno independently discloses the claimed invention. Mizuno describes an integrated circuit with multiple "circuit blocks" (claimed "power islands") whose power is controlled via leakage reduction circuits. These circuits include a "power switch PSW1" (claimed "sleep transistor") that is turned on and off by a "power switch controller PSC" (claimed "sleep generator"). The PSC, in turn, is controlled by a "power controlling circuit PMG" (claimed "adaptive leakage controller") via a request signal REQ. This signal dynamically changes the voltage supplied to the circuit block, reducing leakage current during standby mode. Petitioner contended that Mizuno's disclosure of multiple circuit blocks, each with its own leakage control circuit, teaches the "plurality of power islands."
- Motivation to Combine (for §103 grounds): Not applicable (single reference ground).
- Expectation of Success (for §103 grounds): Not applicable (single reference ground).

Petitioner asserted additional obviousness challenges, including that claims 8 and 15 are obvious over Takahashi in view of Notani (Patent 6,556,071) and over Mizuno in view of Notani, arguing Notani teaches using a charge pump for the sleep generator, which would have been an obvious design choice to implement in the systems of Takahashi or Mizuno.

Petitioner argued that discretionary denial would be inappropriate under both 35 U.S.C. §325(d) and §314(a).
§325(d) (Advanced Bionics): Petitioner asserted that the primary references (Takahashi, Mizuno, Schutz, Notani) were not cited or considered during prosecution, and the arguments presented are not the same or substantially similar to those previously before the Office.
§314(a) (Fintiv): In light of a co-pending district court case, Petitioner argued against discretionary denial under the Fintiv factors by noting it has filed a Sotera stipulation. This stipulation agrees not to pursue in the district court any invalidity grounds that were raised or could have reasonably been raised in the IPR, which Petitioner contended eliminates any risk of duplicative efforts or inconsistent results.

Petitioner requests institution of an inter partes review and cancellation of claims 1-4 and 6-16 of the ’349 patent as unpatentable.