Texas Instruments Inc v. Greenthread LLC

1. Case Identification

• Case #: IPR2024-00772
• Patent #: 10,734,481
• Filed: April 10, 2024
• Petitioner(s): Texas Instruments Incorporated
• Patent Owner(s): Greenthread LLC
• Challenged Claims: 1-9, 12-27, 30-36

2. Patent Overview

• Title: Semiconductor Device Having Graded Dopant Concentrations
• Brief Description: The ’481 patent discloses a semiconductor device featuring graded dopant concentrations in its active and well regions. This grading is purported to create a built-in electric field that aids the movement of charge carriers toward the substrate, thereby improving device performance and reducing soft errors.

3. Grounds for Unpatentability

Ground I: Obviousness over Kawagoe - Claims 1-9, 12-14, 16-27, and 30-36

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kawagoe, which was not considered during prosecution, teaches every element of the challenged claims. Kawagoe discloses a twin-well CMOS device fabricated on an epitaxial substrate. It explicitly teaches that the well regions (e.g., p-well 6p) have a graded dopant concentration that is "gradually lowered in the depthwise direction." This downward-sloping concentration gradient is disclosed to aid carrier movement by attracting unwanted electrons (generated by alpha-ray strikes) to the substrate body, which reduces soft errors in devices like DRAMs. This directly maps to the key limitations of independent claims 1 and 20, including the substrate with first and second surfaces, the active and well regions, and the graded dopant profile for aiding carrier movement from the first surface to the second surface.
  • Motivation to Combine (Embodiments): The challenge relied on combining teachings from different embodiments within Kawagoe. Petitioner asserted a person of ordinary skill in the art (POSITA) would be motivated to use the uniformly-doped epitaxial substrate of Kawagoe's Embodiment 1 with the twin-well device of Embodiment 4. The stated motivations were to reduce manufacturing costs and improve device reliability and performance, as the uniformly-doped substrate provided "excellent film quality" and was less expensive than more heavily-doped alternatives.
  • Expectation of Success: A POSITA would have had a high expectation of success, as this involved a simple substitution of one known substrate type for another, both of which were described in Kawagoe for use in forming twin-well CMOS devices with predictable results.

Ground II: Obviousness over Wieczorek and Wolf - Claims 1-2, 4-9, 12-22, 24-27, and 30-36

• Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (a 2000 textbook, Silicon Processing for the VLSI Era).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner contended that Wieczorek describes a conventional prior-art twin-well CMOS device, including N-channel and P-channel transistors. Wieczorek's figures show that the dopant concentration in the well structures is highest at the surface and decreases with depth, thus disclosing the claimed downward-sloping graded dopant concentration in both the channel (active) regions and the underlying well regions. The textbook by Wolf was cited to supply the well-known context that a uniform, lightly doped p-type or n-type substrate is a conventional and suitable choice for forming the twin-well CMOS device described by Wieczorek. Together, these references were argued to teach all limitations of the challenged claims.
  • Motivation to Combine: A POSITA would have been motivated to combine the teachings of Wieczorek and Wolf because Wieczorek describes a conventional CMOS device but does not specify the starting substrate. A POSITA would naturally look to a standard textbook like Wolf to select an "appropriate substrate," which Wolf confirms is a uniform, lightly doped wafer. The combination represents the assembly of known, compatible components to create a conventional device.
  • Expectation of Success: There was a reasonable expectation of success because the combination involved applying a standard substrate described by Wolf to a conventional CMOS process described by Wieczorek to produce a predictable, widely-used device structure.

• Additional Grounds: Petitioner asserted four additional grounds that build upon the two primary combinations:

  • Grounds III and IV added Gupta (Patent 6,163,877) to the Kawagoe and Wieczorek-Wolf combinations, respectively. Gupta was cited for its teaching of optimizing circuit layouts to include a plurality of transistors in a single active region to conserve chip area, a primary goal in semiconductor design. This was argued to render obvious claims requiring multiple transistors.
  • Grounds V and VI added Silverbrook (Patent 6,614,560) to the Kawagoe and Wieczorek-Wolf combinations, respectively. Silverbrook discloses a CMOS image sensor that incorporates various CMOS logic and memory components. It was cited to show the motivation to implement the general-purpose CMOS designs of the primary references in an image sensor, rendering claims 19 and 36 obvious.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §314(a) and §325(d). For §314(a) and the Fintiv factors, Petitioner asserted that it had eliminated the risk of duplicative efforts in parallel district court litigation by presenting a Sotera stipulation to the Patent Owner. For §325(d), Petitioner argued that the asserted prior art references (Kawagoe, Wieczorek, Wolf, Gupta, and Silverbrook) were neither cited nor considered during the original prosecution of the ’481 patent. Therefore, the arguments presented in the petition were not the same or substantially the same as any previously considered by the USPTO, making discretionary denial inappropriate.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-9, 12-27, and 30-36 of the ’481 patent as unpatentable.