Texas Instruments Inc v. Greenthread LLC

1. Case Identification

• Case #: IPR2024-00773
• Patent #: 9,190,502
• Filed: April 10, 2024
• Petitioner(s): Texas Instruments Incorporated
• Patent Owner(s): Greenthread LLC
• Challenged Claims: 7-12

2. Patent Overview

• Title: Semiconductor Device Having Graded Dopant Concentration and Method of Manufacture
• Brief Description: The ’502 patent relates to a Complementary Metal-Oxide Semiconductor (CMOS) device with graded dopant concentrations in a single drift layer and a well region. This grading is intended to create electric fields that aid the movement of minority carriers from the device's surface layer toward the substrate, purportedly improving device performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Payne - Claim 7 is obvious over Payne.

• Prior Art Relied Upon: Payne (Patent 4,684,971).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Payne teaches all limitations of claim 7. Payne’s nested well structure, comprising a deep "tub region" (e.g., tub 15) and a shallow "surface region" (e.g., region 18) disposed within it, corresponds to the claimed "single drift layer" containing a "well region." Petitioner asserted that Payne's disclosed "high-low implant profile" for creating these regions results in a downward-sloping, graded dopant concentration. Relying on admissions made by the patent owner during prosecution of a parent patent, Petitioner contended this known type of graded profile inherently creates a "first static unidirectional electric drift field" in the drift layer and a "second" field in the well region, both of which aid the movement of minority carriers toward the substrate as claimed.
  • Motivation to Combine (for §103 grounds): Not applicable; this ground is based on a single reference.
  • Expectation of Success (for §103 grounds): Not applicable.

Ground 2: Anticipation/Obviousness over Onoda - Claims 7, 8, and 11 are anticipated or rendered obvious by Onoda.

• Prior Art Relied Upon: Onoda (Japanese Application H8-279598).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Onoda discloses a semiconductor structure meeting all limitations of claims 7, 8, and 11. Onoda’s second semiconductor layer (102), formed via epitaxial deposition, was identified as the claimed single drift layer. Within this layer, Onoda forms various P-wells and N-wells (e.g., 105a), which constitute the claimed "well region." The fabrication process, involving ion implantation and thermal diffusion, results in a dopant profile that "falls off smoothly," creating the claimed graded concentration and the resulting static electric fields. For claim 8, Petitioner asserted Onoda expressly teaches forming a plurality of transistors within a single well region. For claim 11, Onoda explicitly discloses its invention is a "flash memory" device.
  • Motivation to Combine (for §103 grounds): Not applicable.
  • Expectation of Success (for §103 grounds): Not applicable.

Ground 3: Obviousness over Payne and Parrillo - Claim 8 is obvious over Payne in view of Parrillo.

• Prior Art Relied Upon: Payne (Patent 4,684,971) and Parrillo (Patent 4,435,896).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground asserted that Payne teaches the base structure of claim 7, featuring a nested well with graded dopants that create electric fields to aid carrier movement. Parrillo, a contemporaneous patent sharing an inventor and assignee with Payne, disclosed twin-tub CMOS devices for VLSI circuits where each tub contains multiple transistors. The combination allegedly teaches adapting Payne's structure to include multiple active regions within a single well, as required by claim 8.
  • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would combine Payne's improved nested-well structure with Parrillo's known multi-transistor tubs. The motivation was to apply Payne's technique for achieving higher packing density to the known VLSI devices of Parrillo, which already utilized multiple transistors per well.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success because the references are closely related, address similar twin-tub technology, and Payne's improvements were designed for such structures.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations of Payne/Wolf, Onoda/Wolf, Payne/Silverbrook, and Onoda/Silverbrook to invalidate claims 9-12, which add limitations specifying the device is a CPU, DRAM, or image sensor.

4. Key Claim Construction Positions

• Petitioner contended that no special claim constructions were necessary and that the challenged claims are unpatentable under their plain and ordinary meaning.
• However, Petitioner noted that the Patent Owner had previously proposed constructions in related litigation for terms including:
  • "active region": "a doped silicon region at the surface of a semiconductor device where a transistor can be formed"
  • "well region": "a doped region that surrounds the active region of a semiconductor device"
• Petitioner argued its invalidity positions hold even under the Patent Owner's proposed constructions.

5. Arguments Regarding Discretionary Denial

• §314(a) (Fintiv): Petitioner argued against discretionary denial under Fintiv, stating it has eliminated the risk of duplicative effort by voluntarily presenting a Sotera stipulation to the Patent Owner. This stipulation would bar Petitioner from pursuing the same invalidity grounds in the parallel district court litigation.
• §325(d): Petitioner argued that denial under §325(d) is unwarranted because the primary prior art references (Payne and Onoda) were never presented to or considered by the Examiner during prosecution. Petitioner further contended that this art is not cumulative to the art of record (e.g., Rhodes), as Payne and Onoda teach a distinct nested-well structure formed through separate implant and annealing steps, which was the basis for allowance over the prior art.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 7-12 of the ’502 patent as unpatentable.