Texas Instruments Inc v. Greenthread LLC

1. Case Identification

• Case #: IPR2024-00774
• Patent #: 11,316,014
• Filed: April 10, 2024
• Petitioner(s): Texas Instruments Incorporated
• Patent Owner(s): Greenthread LLC
• Challenged Claims: 1-9, 12-28

2. Patent Overview

• Title: Semiconductor Device with Graded Dopant Concentration
• Brief Description: The ’014 patent is directed to an electronic system comprising a semiconductor device with graded dopant concentrations in its active and well regions. This graded doping is purported to create an electric field that aids carrier movement away from the device surface and into the substrate.

3. Grounds for Unpatentability

Ground I: Claims 1-9, 12-14, 16-21, and 23-28 are obvious over Kawagoe.

• Prior Art Relied Upon: Kawagoe (Patent 6,043,114).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kawagoe, which teaches semiconductor integrated circuit devices, disclosed every element of the challenged claims. Specifically, Petitioner focused on Kawagoe’s twin-well CMOS device (Fig. 23), which includes a substrate, first and second active regions containing NMOS and PMOS transistors, and underlying p-wells and n-wells. Critically, Petitioner asserted that Kawagoe’s doping concentration profile (Fig. 17) is "gradually lowered in the depthwise direction," directly mapping to the "graded dopant concentration" limitation. Kawagoe explicitly taught that this downward-sloping gradient serves to attract charge carriers (electrons) into the substrate body to reduce soft errors in devices like DRAMs, thereby meeting the limitation of aiding carrier movement away from the surface.
  • Motivation to Combine: While this is a single-reference ground, Petitioner argued a POSITA would have been motivated to combine features from different embodiments within Kawagoe. Specifically, a POSITA would combine the twin-well CMOS device of Embodiment 4 with the uniformly-doped epitaxial substrate of Embodiment 1. Kawagoe provided the motivation by teaching that this combination lowered manufacturing costs and produced devices with "excellent film quality," improved performance, and higher production yield compared to other substrate options.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success because Kawagoe described both uniformly-doped and latchup-resistant substrates for forming its CMOS devices and repeatedly emphasized their similarity and the predictable effects of using either. The substitution of one known substrate for another in the same reference was presented as a simple design choice with predictable outcomes.

Ground II: Claims 1-2, 4-9, 12-23, and 25-28 are obvious over Wieczorek in view of Wolf.

• Prior Art Relied Upon: Wieczorek (Application # 2003/0183856) and Wolf (Silicon Processing for the VLSI Era, 2000).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner contended that Wieczorek’s disclosure of a conventional twin-well CMOS device taught the core structural elements of the claims, including a substrate supporting first and second active regions (with NMOS and PMOS transistors) within respective P-wells and N-wells. Wieczorek’s dopant profile graph (Fig. 2b) showed a concentration that is highest at the device surface and decreases with depth, which Petitioner mapped to the "graded dopant concentration" limitation. This downward slope was known in the art to create a "built-in" electric field that moves charge carriers deeper into the substrate, thus aiding carrier movement.
  • Motivation to Combine: Wieczorek taught forming its device on an "appropriate substrate" but did not specify the type. Petitioner argued a POSITA would have been motivated to consult a well-known textbook like Wolf for details on conventional CMOS manufacturing. Wolf taught that twin-well CMOS devices, like Wieczorek's, were commonly fabricated on a "uniform, lightly doped p- or n-type substrate." Combining Wolf's conventional substrate with Wieczorek's conventional device was presented as an obvious application of known elements to achieve a predictable result.
  • Expectation of Success: A POSITA would have had a high expectation of success, as Wolf provided a standard, widely-used substrate for the exact type of device described in Wieczorek. The combination represented a routine implementation of a standard CMOS manufacturing process.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on combining the primary references (Kawagoe or Wieczorek-Wolf) with Gupta (Patent 6,163,877) to explicitly teach a plurality of transistors in each active region for high packing density, and with Silverbrook (Patent 6,614,560) to teach the obvious implementation of the claimed semiconductor device within an image sensor.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial would be unjust. To counter denial under §314(a) and the Fintiv factors, Petitioner noted it had voluntarily presented a Sotera stipulation to the Patent Owner, promising not to pursue the same grounds or any reasonably assertable grounds in the parallel district court proceeding, thereby eliminating any risk of duplicative effort.
• Regarding §325(d), Petitioner argued denial is unwarranted because the primary prior art references (Kawagoe, Gupta, Silverbrook, and most volumes of Wolf) were not before the USPTO during prosecution of the ’014 patent. Petitioner asserted that the new references and arguments are not cumulative to what the examiner previously considered.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-9 and 12-28 as unpatentable under 35 U.S.C. §103.